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Aleksandar BeserminjiAleksandar Beserminji
Aleksandar Beserminji
authored and
Aleksandar Beserminji
committedSep 29, 2017
[mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314497
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9 files changed

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-36
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9 files changed

+93
-36
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‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 20 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2992,16 +2992,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
29922992
if (IsTailCall)
29932993
++NumTailCalls;
29942994

2995-
// Chain is the output chain of the last Load/Store or CopyToReg node.
2996-
// ByValChain is the output chain of the last Memcpy node created for copying
2997-
// byval arguments to the stack.
2998-
unsigned StackAlignment = TFL->getStackAlignment();
2999-
NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3000-
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3001-
3002-
if (!IsTailCall)
3003-
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3004-
30052995
SDValue StackPtr =
30062996
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
30072997
getPointerTy(DAG.getDataLayout()));
@@ -3030,7 +3020,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
30303020
assert(ByValIdx < CCInfo.getInRegsParamsCount());
30313021
assert(!IsTailCall &&
30323022
"Do not tail-call optimize if there is a byval argument.");
3033-
passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3023+
Chain = passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
30343024
FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
30353025
VA);
30363026
CCInfo.nextInRegsParam();
@@ -3122,6 +3112,16 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
31223112
EVT Ty = Callee.getValueType();
31233113
bool GlobalOrExternal = false, IsCallReloc = false;
31243114

3115+
// Chain is the output chain of the last Load/Store or CopyToReg node.
3116+
// ByValChain is the output chain of the last Memcpy node created for copying
3117+
// byval arguments to the stack.
3118+
unsigned StackAlignment = TFL->getStackAlignment();
3119+
NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3120+
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3121+
3122+
if (!IsTailCall)
3123+
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3124+
31253125
// The long-calls feature is ignored in case of PIC.
31263126
// While we do not support -mshared / -mno-shared properly,
31273127
// ignore long-calls in case of -mabicalls too.
@@ -4095,7 +4095,7 @@ void MipsTargetLowering::copyByValRegs(
40954095
}
40964096

40974097
// Copy byVal arg to registers and stack.
4098-
void MipsTargetLowering::passByValArg(
4098+
SDValue MipsTargetLowering::passByValArg(
40994099
SDValue Chain, const SDLoc &DL,
41004100
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
41014101
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
@@ -4128,7 +4128,7 @@ void MipsTargetLowering::passByValArg(
41284128

41294129
// Return if the struct has been fully copied.
41304130
if (ByValSizeInBytes == OffsetInBytes)
4131-
return;
4131+
return Chain;
41324132

41334133
// Copy the remainder of the byval argument with sub-word loads and shifts.
41344134
if (LeftoverBytes) {
@@ -4173,7 +4173,7 @@ void MipsTargetLowering::passByValArg(
41734173

41744174
unsigned ArgReg = ArgRegs[FirstReg + I];
41754175
RegsToPass.push_back(std::make_pair(ArgReg, Val));
4176-
return;
4176+
return Chain;
41774177
}
41784178
}
41794179

@@ -4183,12 +4183,13 @@ void MipsTargetLowering::passByValArg(
41834183
DAG.getConstant(OffsetInBytes, DL, PtrTy));
41844184
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
41854185
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4186-
Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4187-
DAG.getConstant(MemCpySize, DL, PtrTy),
4188-
Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4189-
/*isTailCall=*/false,
4190-
MachinePointerInfo(), MachinePointerInfo());
4186+
Chain = DAG.getMemcpy(
4187+
Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment,
4188+
/*isVolatile=*/false, /*AlwaysInline=*/false,
4189+
/*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
41914190
MemOpChains.push_back(Chain);
4191+
4192+
return Chain;
41924193
}
41934194

41944195
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,

‎llvm/lib/Target/Mips/MipsISelLowering.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -573,13 +573,13 @@ class TargetRegisterClass;
573573
MipsCCState &State) const;
574574

575575
/// passByValArg - Pass a byval argument in registers or on stack.
576-
void passByValArg(SDValue Chain, const SDLoc &DL,
577-
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
578-
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
579-
MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
580-
unsigned FirstReg, unsigned LastReg,
581-
const ISD::ArgFlagsTy &Flags, bool isLittle,
582-
const CCValAssign &VA) const;
576+
SDValue passByValArg(SDValue Chain, const SDLoc &DL,
577+
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
578+
SmallVectorImpl<SDValue> &MemOpChains,
579+
SDValue StackPtr, MachineFrameInfo &MFI,
580+
SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
581+
unsigned LastReg, const ISD::ArgFlagsTy &Flags,
582+
bool isLittle, const CCValAssign &VA) const;
583583

584584
/// writeVarArgRegs - Write variable function arguments passed in registers
585585
/// to the stack. Also create a stack frame object for the first variable

‎llvm/test/CodeGen/Mips/callseq_order.ll

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
; RUN: llc -mtriple=mipsel-linux-gnu -o /dev/null \
2+
; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
3+
; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
4+
; RUN: llc -mtriple=mips64el-linux-gnu -o /dev/null \
5+
; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
6+
; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
7+
; RUN: llc -mtriple=mips-linux-gnu -o /dev/null \
8+
; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
9+
; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
10+
; RUN: llc -mtriple=mips64-linux-gnu -o /dev/null \
11+
; RUN: -verify-machineinstrs -stop-before=expand-isel-pseudos \
12+
; RUN: -debug-only=isel %s 2>&1 | FileCheck %s
13+
14+
15+
%struct.Str1 = type { [64 x i32] }
16+
17+
@s1 = common global %struct.Str1 zeroinitializer, align 4
18+
19+
define void @foo1() {
20+
entry:
21+
call void @bar1(%struct.Str1* byval align 4 @s1)
22+
ret void
23+
; CHECK-LABEL: *** MachineFunction at end of ISel ***
24+
; CHECK-LABEL: # Machine code for function foo1: IsSSA, TracksLiveness
25+
; CHECK: ADJCALLSTACKDOWN
26+
; CHECK: JAL <es:memcpy>
27+
; CHECK: ADJCALLSTACKUP
28+
; CHECK: ADJCALLSTACKDOWN
29+
; CHECK: JAL <ga:@bar1>
30+
; CHECK: ADJCALLSTACKUP
31+
; CHECK-LABEL: # End machine code for function foo1.
32+
}
33+
34+
declare void @bar1(%struct.Str1* byval align 4)
35+
36+
define void @foo2() {
37+
entry:
38+
call void @bar2(%struct.Str1* byval align 4 @s1, %struct.Str1* byval align 4 @s1)
39+
ret void
40+
; CHECK-LABEL: *** MachineFunction at end of ISel ***
41+
; CHECK-LABEL: # Machine code for function foo2: IsSSA, TracksLiveness
42+
; CHECK: ADJCALLSTACKDOWN
43+
; CHECK: JAL <es:memcpy>
44+
; CHECK: ADJCALLSTACKUP
45+
; CHECK: ADJCALLSTACKDOWN
46+
; CHECK: JAL <es:memcpy>
47+
; CHECK: ADJCALLSTACKUP
48+
; CHECK: ADJCALLSTACKDOWN
49+
; CHECK: JAL <ga:@bar2>
50+
; CHECK: ADJCALLSTACKUP
51+
; CHECK-LABEL: # End machine code for function foo2.
52+
}
53+
54+
declare void @bar2(%struct.Str1* byval align 4, %struct.Str1* byval align 4)
55+

‎llvm/test/CodeGen/Mips/largeimmprinting.ll

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
1-
; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
2-
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
3-
; RUN: FileCheck %s -check-prefix=64
4-
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
5-
; RUN: FileCheck %s -check-prefix=64
1+
; RUN: llc -march=mipsel -relocation-model=pic -verify-machineinstrs < %s | \
2+
; RUN: FileCheck %s -check-prefix=32
3+
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic \
4+
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
5+
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
6+
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
67

78
%struct.S1 = type { [65536 x i8] }
89

‎llvm/test/CodeGen/Mips/llvm-ir/mul.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ entry:
268268
; MM64R6: daddu $2, $[[T1]], $[[T0]]
269269
; MM64R6-DAG: dmul $3, $5, $7
270270

271-
; MM32: lw $25, %call16(__multi3)($16)
271+
; MM32: lw $25, %call16(__multi3)
272272

273273
%r = mul i128 %a, %b
274274
ret i128 %r

‎llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ entry:
190190
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
191191
; 64R6: ld $25, %call16(__divti3)($gp)
192192

193-
; MM32: lw $25, %call16(__divti3)($16)
193+
; MM32: lw $25, %call16(__divti3)
194194

195195
; MM64: ld $25, %call16(__divti3)($2)
196196

‎llvm/test/CodeGen/Mips/llvm-ir/srem.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ entry:
182182
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
183183
; 64R6: ld $25, %call16(__modti3)($gp)
184184

185-
; MM32: lw $25, %call16(__modti3)($16)
185+
; MM32: lw $25, %call16(__modti3)
186186

187187
; MM64: ld $25, %call16(__modti3)($2)
188188

‎llvm/test/CodeGen/Mips/llvm-ir/udiv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ entry:
152152
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
153153
; 64-R6: ld $25, %call16(__udivti3)($gp)
154154

155-
; MM32: lw $25, %call16(__udivti3)($16)
155+
; MM32: lw $25, %call16(__udivti3)
156156

157157
; MM64: ld $25, %call16(__udivti3)($2)
158158

‎llvm/test/CodeGen/Mips/llvm-ir/urem.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ entry:
208208
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
209209
; 64R6: ld $25, %call16(__umodti3)($gp)
210210

211-
; MM32: lw $25, %call16(__umodti3)($16)
211+
; MM32: lw $25, %call16(__umodti3)
212212

213213
; MM64: ld $25, %call16(__umodti3)($2)
214214

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