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Commit 00161c9

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committedSep 18, 2017
[X86][SSE] Improve support for vselect(Cond, 0, X) -> ANDN(Cond, X)
As discussed on PR28925 and D37849. Differential Revision: https://reviews.llvm.org/D37975 llvm-svn: 313532
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+25
-23
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3 files changed

+25
-23
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

+14
Original file line numberDiff line numberDiff line change
@@ -30090,6 +30090,7 @@ static SDValue combineExtractVectorElt_SSE(SDNode *N, SelectionDAG &DAG,
3009030090

3009130091
/// If a vector select has an operand that is -1 or 0, try to simplify the
3009230092
/// select to a bitwise logic operation.
30093+
/// TODO: Move to DAGCombiner, possibly using TargetLowering::hasAndNot()?
3009330094
static SDValue
3009430095
combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
3009530096
TargetLowering::DAGCombinerInfo &DCI,
@@ -30153,6 +30154,10 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
3015330154
}
3015430155
}
3015530156

30157+
// Cond value must be 'sign splat' to be converted to a logical op.
30158+
if (DAG.ComputeNumSignBits(Cond) != CondVT.getScalarSizeInBits())
30159+
return SDValue();
30160+
3015630161
// vselect Cond, 111..., 000... -> Cond
3015730162
if (TValIsAllOnes && FValIsAllZeros)
3015830163
return DAG.getBitcast(VT, Cond);
@@ -30174,6 +30179,15 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
3017430179
return DAG.getBitcast(VT, And);
3017530180
}
3017630181

30182+
// vselect Cond, 000..., X -> andn Cond, X
30183+
if (TValIsAllZeros) {
30184+
MVT AndNVT = MVT::getVectorVT(MVT::i64, CondVT.getSizeInBits() / 64);
30185+
SDValue CastCond = DAG.getBitcast(AndNVT, Cond);
30186+
SDValue CastRHS = DAG.getBitcast(AndNVT, RHS);
30187+
SDValue AndN = DAG.getNode(X86ISD::ANDNP, DL, AndNVT, CastCond, CastRHS);
30188+
return DAG.getBitcast(VT, AndN);
30189+
}
30190+
3017730191
return SDValue();
3017830192
}
3017930193

‎llvm/test/CodeGen/X86/psubus.ll

+3-7
Original file line numberDiff line numberDiff line change
@@ -683,9 +683,7 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind {
683683
; SSE41-NEXT: pand %xmm5, %xmm2
684684
; SSE41-NEXT: packuswb %xmm2, %xmm1
685685
; SSE41-NEXT: packuswb %xmm3, %xmm1
686-
; SSE41-NEXT: pxor %xmm2, %xmm2
687-
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
688-
; SSE41-NEXT: movdqa %xmm1, %xmm0
686+
; SSE41-NEXT: pandn %xmm1, %xmm0
689687
; SSE41-NEXT: retq
690688
;
691689
; AVX1-LABEL: test14:
@@ -727,8 +725,7 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind {
727725
; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm2
728726
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
729727
; AVX1-NEXT: vpackuswb %xmm0, %xmm1, %xmm0
730-
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
731-
; AVX1-NEXT: vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
728+
; AVX1-NEXT: vpandn %xmm0, %xmm3, %xmm0
732729
; AVX1-NEXT: vzeroupper
733730
; AVX1-NEXT: retq
734731
;
@@ -760,8 +757,7 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind {
760757
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
761758
; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
762759
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
763-
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
764-
; AVX2-NEXT: vpblendvb %xmm4, %xmm1, %xmm0, %xmm0
760+
; AVX2-NEXT: vpandn %xmm0, %xmm4, %xmm0
765761
; AVX2-NEXT: vzeroupper
766762
; AVX2-NEXT: retq
767763
vector.ph:

‎llvm/test/CodeGen/X86/vselect-zero.ll

+8-16
Original file line numberDiff line numberDiff line change
@@ -7,26 +7,18 @@
77
; PR28925
88

99
define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
10-
; SSE2-LABEL: test1:
11-
; SSE2: # BB#0:
12-
; SSE2-NEXT: pslld $31, %xmm0
13-
; SSE2-NEXT: psrad $31, %xmm0
14-
; SSE2-NEXT: pandn %xmm1, %xmm0
15-
; SSE2-NEXT: retq
16-
;
17-
; SSE42-LABEL: test1:
18-
; SSE42: # BB#0:
19-
; SSE42-NEXT: pslld $31, %xmm0
20-
; SSE42-NEXT: xorps %xmm2, %xmm2
21-
; SSE42-NEXT: blendvps %xmm0, %xmm2, %xmm1
22-
; SSE42-NEXT: movaps %xmm1, %xmm0
23-
; SSE42-NEXT: retq
10+
; SSE-LABEL: test1:
11+
; SSE: # BB#0:
12+
; SSE-NEXT: pslld $31, %xmm0
13+
; SSE-NEXT: psrad $31, %xmm0
14+
; SSE-NEXT: pandn %xmm1, %xmm0
15+
; SSE-NEXT: retq
2416
;
2517
; AVX-LABEL: test1:
2618
; AVX: # BB#0:
2719
; AVX-NEXT: vpslld $31, %xmm0, %xmm0
28-
; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
29-
; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
20+
; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
21+
; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0
3022
; AVX-NEXT: retq
3123
%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
3224
ret <4 x i32> %r

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