@@ -802,9 +802,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SSUBO, MVT::i32, Custom);
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setOperationAction(ISD::USUBO, MVT::i32, Custom);
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- setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
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- setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
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-
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// i64 operation support.
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::i32, Expand);
@@ -3956,7 +3953,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
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}
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SDValue
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- ARMTargetLowering::LowerSignedALUO (SDValue Op, SelectionDAG &DAG) const {
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+ ARMTargetLowering::LowerXALUO (SDValue Op, SelectionDAG &DAG) const {
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// Let legalize expand this if it isn't a legal type yet.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
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return SDValue();
@@ -3978,66 +3975,6 @@ ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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}
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- static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
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- SelectionDAG &DAG) {
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- SDLoc DL(BoolCarry);
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- EVT CarryVT = BoolCarry.getValueType();
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-
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- APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits());
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- // This converts the boolean value carry into the carry flag by doing
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- // ARMISD::ADDC Carry, ~0
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- return DAG.getNode(ARMISD::ADDC, DL, DAG.getVTList(CarryVT, MVT::i32),
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- BoolCarry, DAG.getConstant(NegOne, DL, CarryVT));
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- }
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-
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- static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
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- SelectionDAG &DAG) {
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- SDLoc DL(Flags);
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-
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- // Now convert the carry flag into a boolean carry. We do this
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- // using ARMISD:ADDE 0, 0, Carry
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- return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
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- DAG.getConstant(0, DL, MVT::i32),
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- DAG.getConstant(0, DL, MVT::i32), Flags);
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- }
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-
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- SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
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- SelectionDAG &DAG) const {
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- // Let legalize expand this if it isn't a legal type yet.
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- if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
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- return SDValue();
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-
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- SDValue LHS = Op.getOperand(0);
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- SDValue RHS = Op.getOperand(1);
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- SDLoc dl(Op);
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-
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- EVT VT = Op.getValueType();
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- SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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- SDValue Value;
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- SDValue Overflow;
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- switch (Op.getOpcode()) {
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- default:
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- llvm_unreachable("Unknown overflow instruction!");
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- case ISD::UADDO:
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- Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
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- // Convert the carry flag into a boolean value.
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- Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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- break;
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- case ISD::USUBO: {
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- Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
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- // Convert the carry flag into a boolean value.
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- Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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- // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
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- // value. So compute 1 - C.
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- Overflow = DAG.getNode(ISD::SUB, dl, VTs,
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- DAG.getConstant(1, dl, MVT::i32), Overflow);
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- break;
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- }
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- }
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-
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- return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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- }
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-
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SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cond = Op.getOperand(0);
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SDValue SelectTrue = Op.getOperand(1);
@@ -7443,53 +7380,6 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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Op.getOperand(1), Op.getOperand(2));
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}
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- static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
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- SDNode *N = Op.getNode();
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- EVT VT = N->getValueType(0);
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- SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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-
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- SDValue Carry = Op.getOperand(2);
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- EVT CarryVT = Carry.getValueType();
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-
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- SDLoc DL(Op);
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-
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- APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits());
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-
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- SDValue Result;
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- if (Op.getOpcode() == ISD::ADDCARRY) {
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- // This converts the boolean value carry into the carry flag.
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- Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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-
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- // Do the addition proper using the carry flag we wanted.
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- Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
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- Op.getOperand(1), Carry.getValue(1));
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-
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- // Now convert the carry flag into a boolean value.
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- Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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- } else {
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- // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
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- // have to invert the carry first.
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- Carry =
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- DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry);
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- // This converts the boolean value carry into the carry flag.
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- Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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-
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- // Do the subtraction proper using the carry flag we wanted.
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- Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
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- Op.getOperand(1), Carry.getValue(1));
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-
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- // Now convert the carry flag into a boolean value.
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- Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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- // But the carry returned by ARMISD::SUBE is not a borrow as expected
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- // by ISD::SUBCARRY, so compute 1 - C.
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- Carry =
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- DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry);
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- }
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-
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- // Return both values.
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- return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry);
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- }
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-
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SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
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assert(Subtarget->isTargetDarwin());
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@@ -7844,14 +7734,11 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ADDE:
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case ISD::SUBC:
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case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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- case ISD::ADDCARRY:
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- case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
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case ISD::SADDO:
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- case ISD::SSUBO:
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- return LowerSignedALUO(Op, DAG);
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case ISD::UADDO:
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+ case ISD::SSUBO:
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case ISD::USUBO:
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- return LowerUnsignedALUO (Op, DAG);
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+ return LowerXALUO (Op, DAG);
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case ISD::ATOMIC_LOAD:
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case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
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case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
@@ -9800,19 +9687,19 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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// a S/UMLAL instruction.
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// UMUL_LOHI
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// / :lo \ :hi
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- // V \ [no multiline comment]
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- // loAdd -> ADDC |
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- // \ :carry /
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- // V V
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- // ADDE <- hiAdd
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+ // / \ [no multiline comment]
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+ // loAdd -> ADDE |
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+ // \ :glue /
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+ // \ /
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+ // ADDC <- hiAdd
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//
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assert(AddeNode->getOpcode() == ARMISD::ADDE && "Expect an ADDE");
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assert(AddeNode->getNumOperands() == 3 &&
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AddeNode->getOperand(2).getValueType() == MVT::i32 &&
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"ADDE node has the wrong inputs");
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- // Check that we are chained to the right ADDC node.
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+ // Check that we have a glued ADDC node.
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SDNode* AddcNode = AddeNode->getOperand(2).getNode();
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if (AddcNode->getOpcode() != ARMISD::ADDC)
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return SDValue();
@@ -9863,7 +9750,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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SDValue* LoMul = nullptr;
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SDValue* LowAdd = nullptr;
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- // Ensure that ADDE is from high result of ISD::xMUL_LOHI .
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+ // Ensure that ADDE is from high result of ISD::SMUL_LOHI .
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if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
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return SDValue();
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@@ -9888,11 +9775,6 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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if (!LoMul)
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return SDValue();
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- // If HiAdd is a predecessor of ADDC, the replacement below will create a
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- // cycle.
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- if (AddcNode->isPredecessorOf(HiAdd->getNode()))
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- return SDValue();
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-
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// Create the merged node.
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SelectionDAG &DAG = DCI.DAG;
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@@ -9995,22 +9877,8 @@ static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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- static SDValue PerformAddcSubcCombine(SDNode *N,
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- TargetLowering::DAGCombinerInfo &DCI,
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+ static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) {
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- SelectionDAG &DAG(DCI.DAG);
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-
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- if (N->getOpcode() == ARMISD::ADDC) {
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- // (ADDC (ADDE 0, 0, C), -1) -> C
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- SDValue LHS = N->getOperand(0);
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- SDValue RHS = N->getOperand(1);
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- if (LHS->getOpcode() == ARMISD::ADDE &&
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- isNullConstant(LHS->getOperand(0)) &&
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- isNullConstant(LHS->getOperand(1)) && isAllOnesConstant(RHS)) {
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- return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
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- }
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- }
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-
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if (Subtarget->isThumb1Only()) {
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SDValue RHS = N->getOperand(1);
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
@@ -11899,14 +11767,6 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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- static const APInt *isPowerOf2Constant(SDValue V) {
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- ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
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- if (!C)
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- return nullptr;
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- const APInt *CV = &C->getAPIntValue();
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- return CV->isPowerOf2() ? CV : nullptr;
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- }
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-
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SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
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// If we have a CMOV, OR and AND combination such as:
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// if (x & CN)
@@ -11935,8 +11795,8 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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SDValue And = CmpZ->getOperand(0);
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if (And->getOpcode() != ISD::AND)
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return SDValue();
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- const APInt *AndC = isPowerOf2Constant (And->getOperand(1));
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- if (!AndC)
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+ ConstantSDNode *AndC = dyn_cast<ConstantSDNode> (And->getOperand(1));
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+ if (!AndC || !AndC->getAPIntValue().isPowerOf2() )
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return SDValue();
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SDValue X = And->getOperand(0);
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@@ -11976,7 +11836,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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SDValue V = Y;
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SDLoc dl(X);
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EVT VT = X.getValueType();
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- unsigned BitInX = AndC->logBase2();
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+ unsigned BitInX = AndC->getAPIntValue(). logBase2();
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if (BitInX != 0) {
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// We must shift X first.
@@ -12137,7 +11997,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
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case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
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case ARMISD::ADDC:
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- case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget);
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+ case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI.DAG , Subtarget);
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case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
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case ARMISD::BFI: return PerformBFICombine(N, DCI);
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case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
@@ -12833,17 +12693,10 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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case ARMISD::ADDE:
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case ARMISD::SUBC:
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case ARMISD::SUBE:
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- // Special cases when we convert a carry to a boolean.
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- if (Op.getResNo() == 0) {
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- SDValue LHS = Op.getOperand(0);
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- SDValue RHS = Op.getOperand(1);
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- // (ADDE 0, 0, C) will give us a single bit.
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- if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) &&
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- isNullConstant(RHS)) {
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- Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
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- return;
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- }
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- }
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+ // These nodes' second result is a boolean
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+ if (Op.getResNo() == 0)
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+ break;
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+ Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
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break;
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case ARMISD::CMOV: {
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// Bits are known zero/one if known on the LHS and RHS.
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