[X86] Remove memopmmx pattern fragment

topperc · topperc · commit 5960848060d1 · 2017-08-17T15:25:05.000Z
Summary: Just like the FIXME says, there is no alignment requirement for MMX. Reviewers: RKSimon, zvi, igorb Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36815 llvm-svn: 311090
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -761,15 +761,6 @@ def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 
-// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
-// 16-byte boundary.
-// FIXME: 8 byte alignment for mmx reads is not required
-def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
-  return cast<LoadSDNode>(N)->getAlignment() >= 8;
-}]>;
-
-def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
-
 def X86masked_gather  : SDNode<"X86ISD::MGATHER",  SDTMaskedGather,
                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -143,7 +143,7 @@ multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
   def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
                    [(set VR64:$dst,
-                     (IntId64 (bitconvert (memopmmx addr:$src))))],
+                     (IntId64 (bitconvert (load_mmx addr:$src))))],
                    itins.rm>, Sched<[itins.Sched.Folded]>;
 }
 
@@ -163,7 +163,7 @@ multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
        [(set VR64:$dst,
          (IntId64 VR64:$src1,
-          (bitconvert (memopmmx addr:$src2))))], itins.rm>,
+          (bitconvert (load_mmx addr:$src2))))], itins.rm>,
       Sched<[itins.Sched.Folded, ReadAfterLd]>;
 }
 }

Original file line number	Diff line number	Diff line change
`@@ -143,7 +143,7 @@ multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,`
`143`	`143`	`def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),`
`144`	`144`	`!strconcat(OpcodeStr, "\t{$src, $dst\|$dst, $src}"),`
`145`	`145`	`[(set VR64:$dst,`
`146`		`- (IntId64 (bitconvert (memopmmx addr:$src))))],`
	`146`	`+ (IntId64 (bitconvert (load_mmx addr:$src))))],`
`147`	`147`	`itins.rm>, Sched<[itins.Sched.Folded]>;`
`148`	`148`	`}`
`149`	`149`
`@@ -163,7 +163,7 @@ multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,`
`163`	`163`	`!strconcat(OpcodeStr, "\t{$src2, $dst\|$dst, $src2}"),`
`164`	`164`	`[(set VR64:$dst,`
`165`	`165`	`(IntId64 VR64:$src1,`
`166`		`- (bitconvert (memopmmx addr:$src2))))], itins.rm>,`
	`166`	`+ (bitconvert (load_mmx addr:$src2))))], itins.rm>,`
`167`	`167`	`Sched<[itins.Sched.Folded, ReadAfterLd]>;`
`168`	`168`	`}`
`169`	`169`	`}`