[InstCombine] Propagate nsw flag when turning mul by pow2 into shift when the constant is a vector splat or the scalar bit width is larger than 64-bits

topperc · topperc · commit 5fe019762210 · 2017-06-27T19:57:53.000Z
The check to see if we can propagate the nsw flag used m_ConstantInt(uint64_t*&) which doesn't work with splat vectors and has a restriction that the bitwidth of the ConstantInt must be 64-bits are less. This patch changes it to use m_APInt to remove both these issues Differential Revision: https://reviews.llvm.org/D34699 llvm-svn: 306457
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -227,8 +227,8 @@ Instruction *InstCombiner::visitMul(BinaryOperator &I) {
         if (I.hasNoUnsignedWrap())
           Shl->setHasNoUnsignedWrap();
         if (I.hasNoSignedWrap()) {
-          uint64_t V;
-          if (match(NewCst, m_ConstantInt(V)) && V != Width - 1)
+          const APInt *V;
+          if (match(NewCst, m_APInt(V)) && *V != Width - 1)
             Shl->setHasNoSignedWrap();
         }
 
diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll
@@ -300,7 +300,7 @@ define i32 @test32(i32 %X) {
 
 define <2 x i32> @test32vec(<2 x i32> %X) {
 ; CHECK-LABEL: @test32vec(
-; CHECK-NEXT:    [[MUL:%.*]] = shl <2 x i32> [[X:%.*]], <i32 31, i32 31>
+; CHECK-NEXT:    [[MUL:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 31, i32 31>
 ; CHECK-NEXT:    ret <2 x i32> [[MUL]]
 ;
   %mul = mul nsw <2 x i32> %X, <i32 -2147483648, i32 -2147483648>
@@ -315,20 +315,18 @@ define i32 @test33(i32 %X) {
   ret i32 %mul
 }
 
-; TODO: we should propagate nsw flag to the shift here
 define <2 x i32> @test33vec(<2 x i32> %X) {
 ; CHECK-LABEL: @test33vec(
-; CHECK-NEXT:    [[MUL:%.*]] = shl <2 x i32> [[X:%.*]], <i32 30, i32 30>
+; CHECK-NEXT:    [[MUL:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 30, i32 30>
 ; CHECK-NEXT:    ret <2 x i32> [[MUL]]
 ;
   %mul = mul nsw <2 x i32> %X, <i32 1073741824, i32 1073741824>
   ret <2 x i32> %mul
 }
 
-; TODO: we should propagate nsw flag to the shift here, but we only handle i64 and smaller
 define i128 @test34(i128 %X) {
 ; CHECK-LABEL: @test34(
-; CHECK-NEXT:    [[MUL:%.*]] = shl i128 [[X:%.*]], 1
+; CHECK-NEXT:    [[MUL:%.*]] = shl nsw i128 [[X:%.*]], 1
 ; CHECK-NEXT:    ret i128 [[MUL]]
 ;
   %mul = mul nsw i128 %X, 2

Original file line number	Diff line number	Diff line change
`@@ -300,7 +300,7 @@ define i32 @test32(i32 %X) {`
`300`	`300`
`301`	`301`	`define <2 x i32> @test32vec(<2 x i32> %X) {`
`302`	`302`	`; CHECK-LABEL: @test32vec(`
`303`		`-; CHECK-NEXT: [[MUL:%.]] = shl <2 x i32> [[X:%.]], <i32 31, i32 31>`
	`303`	`+; CHECK-NEXT: [[MUL:%.]] = shl nsw <2 x i32> [[X:%.]], <i32 31, i32 31>`
`304`	`304`	`; CHECK-NEXT: ret <2 x i32> [[MUL]]`
`305`	`305`	`;`
`306`	`306`	`%mul = mul nsw <2 x i32> %X, <i32 -2147483648, i32 -2147483648>`
`@@ -315,20 +315,18 @@ define i32 @test33(i32 %X) {`
`315`	`315`	`ret i32 %mul`
`316`	`316`	`}`
`317`	`317`
`318`		`-; TODO: we should propagate nsw flag to the shift here`
`319`	`318`	`define <2 x i32> @test33vec(<2 x i32> %X) {`
`320`	`319`	`; CHECK-LABEL: @test33vec(`
`321`		`-; CHECK-NEXT: [[MUL:%.]] = shl <2 x i32> [[X:%.]], <i32 30, i32 30>`
	`320`	`+; CHECK-NEXT: [[MUL:%.]] = shl nsw <2 x i32> [[X:%.]], <i32 30, i32 30>`
`322`	`321`	`; CHECK-NEXT: ret <2 x i32> [[MUL]]`
`323`	`322`	`;`
`324`	`323`	`%mul = mul nsw <2 x i32> %X, <i32 1073741824, i32 1073741824>`
`325`	`324`	`ret <2 x i32> %mul`
`326`	`325`	`}`
`327`	`326`
`328`		`-; TODO: we should propagate nsw flag to the shift here, but we only handle i64 and smaller`
`329`	`327`	`define i128 @test34(i128 %X) {`
`330`	`328`	`; CHECK-LABEL: @test34(`
`331`		`-; CHECK-NEXT: [[MUL:%.]] = shl i128 [[X:%.]], 1`
	`329`	`+; CHECK-NEXT: [[MUL:%.]] = shl nsw i128 [[X:%.]], 1`
`332`	`330`	`; CHECK-NEXT: ret i128 [[MUL]]`
`333`	`331`	`;`
`334`	`332`	`%mul = mul nsw i128 %X, 2`