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fhahnfhahn
committedMay 24, 2017
[ARM] Remove ThumbTargetMachines. (NFC)
Summary: Thumb code generation is controlled by ARMSubtarget and the concrete ThumbLETargetMachine and ThumbBETargetMachine are not needed. Eric Christopher suggested removing the unneeded target machines in https://reviews.llvm.org/D33287. I think it still makes sense to keep separate TargetMachines for big and little endian as we probably do not want to have different endianess for difference functions in a single compilation unit. The MIPS backend has two separate TargetMachines for big and little endian as well. Reviewers: echristo, rengolin, kristof.beyls, t.p.northover Reviewed By: echristo Subscribers: aemerson, javed.absar, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D33318 llvm-svn: 303733
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llvmorg-21-initllvmorg-5.0.0-rc1
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3 files changed

+15
-114
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3 files changed

+15
-114
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‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

+9-54
Original file line numberDiff line numberDiff line change
@@ -85,9 +85,9 @@ namespace llvm {
8585
extern "C" void LLVMInitializeARMTarget() {
8686
// Register the target.
8787
RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
88+
RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
8889
RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
89-
RegisterTargetMachine<ThumbLETargetMachine> A(getTheThumbLETarget());
90-
RegisterTargetMachine<ThumbBETargetMachine> B(getTheThumbBETarget());
90+
RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
9191

9292
PassRegistry &Registry = *PassRegistry::getPassRegistry();
9393
initializeGlobalISel(Registry);
@@ -263,6 +263,11 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
263263
else
264264
this->Options.EABIVersion = EABI::EABI5;
265265
}
266+
267+
initAsmInfo();
268+
if (!Subtarget.isThumb() && !Subtarget.hasARMOps())
269+
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
270+
"support ARM mode execution!");
266271
}
267272

268273
ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
@@ -355,72 +360,22 @@ TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
355360
});
356361
}
357362

358-
void ARMTargetMachine::anchor() {}
359-
360-
ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
361-
StringRef CPU, StringRef FS,
362-
const TargetOptions &Options,
363-
Optional<Reloc::Model> RM,
364-
CodeModel::Model CM, CodeGenOpt::Level OL,
365-
bool isLittle)
366-
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
367-
initAsmInfo();
368-
if (!Subtarget.hasARMOps())
369-
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
370-
"support ARM mode execution!");
371-
}
372-
373-
void ARMLETargetMachine::anchor() {}
374363

375364
ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
376365
StringRef CPU, StringRef FS,
377366
const TargetOptions &Options,
378367
Optional<Reloc::Model> RM,
379368
CodeModel::Model CM,
380369
CodeGenOpt::Level OL)
381-
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
382-
383-
void ARMBETargetMachine::anchor() {}
370+
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
384371

385372
ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
386373
StringRef CPU, StringRef FS,
387374
const TargetOptions &Options,
388375
Optional<Reloc::Model> RM,
389376
CodeModel::Model CM,
390377
CodeGenOpt::Level OL)
391-
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
392-
393-
void ThumbTargetMachine::anchor() {}
394-
395-
ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
396-
StringRef CPU, StringRef FS,
397-
const TargetOptions &Options,
398-
Optional<Reloc::Model> RM,
399-
CodeModel::Model CM,
400-
CodeGenOpt::Level OL, bool isLittle)
401-
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
402-
initAsmInfo();
403-
}
404-
405-
void ThumbLETargetMachine::anchor() {}
406-
407-
ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
408-
StringRef CPU, StringRef FS,
409-
const TargetOptions &Options,
410-
Optional<Reloc::Model> RM,
411-
CodeModel::Model CM,
412-
CodeGenOpt::Level OL)
413-
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
414-
415-
void ThumbBETargetMachine::anchor() {}
416-
417-
ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
418-
StringRef CPU, StringRef FS,
419-
const TargetOptions &Options,
420-
Optional<Reloc::Model> RM,
421-
CodeModel::Model CM,
422-
CodeGenOpt::Level OL)
423-
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
378+
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
424379

425380
namespace {
426381

‎llvm/lib/Target/ARM/ARMTargetMachine.h

+4-58
Original file line numberDiff line numberDiff line change
@@ -62,80 +62,26 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
6262
}
6363
};
6464

65-
/// ARM target machine.
65+
/// ARM/Thumb little endian target machine.
6666
///
67-
class ARMTargetMachine : public ARMBaseTargetMachine {
68-
virtual void anchor();
69-
70-
public:
71-
ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
72-
StringRef FS, const TargetOptions &Options,
73-
Optional<Reloc::Model> RM, CodeModel::Model CM,
74-
CodeGenOpt::Level OL, bool isLittle);
75-
};
76-
77-
/// ARM little endian target machine.
78-
///
79-
class ARMLETargetMachine : public ARMTargetMachine {
80-
void anchor() override;
81-
67+
class ARMLETargetMachine : public ARMBaseTargetMachine {
8268
public:
8369
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
8470
StringRef FS, const TargetOptions &Options,
8571
Optional<Reloc::Model> RM, CodeModel::Model CM,
8672
CodeGenOpt::Level OL);
8773
};
8874

89-
/// ARM big endian target machine.
75+
/// ARM/Thumb big endian target machine.
9076
///
91-
class ARMBETargetMachine : public ARMTargetMachine {
92-
void anchor() override;
93-
77+
class ARMBETargetMachine : public ARMBaseTargetMachine {
9478
public:
9579
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
9680
StringRef FS, const TargetOptions &Options,
9781
Optional<Reloc::Model> RM, CodeModel::Model CM,
9882
CodeGenOpt::Level OL);
9983
};
10084

101-
/// Thumb target machine.
102-
/// Due to the way architectures are handled, this represents both
103-
/// Thumb-1 and Thumb-2.
104-
///
105-
class ThumbTargetMachine : public ARMBaseTargetMachine {
106-
virtual void anchor();
107-
108-
public:
109-
ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
110-
StringRef FS, const TargetOptions &Options,
111-
Optional<Reloc::Model> RM, CodeModel::Model CM,
112-
CodeGenOpt::Level OL, bool isLittle);
113-
};
114-
115-
/// Thumb little endian target machine.
116-
///
117-
class ThumbLETargetMachine : public ThumbTargetMachine {
118-
void anchor() override;
119-
120-
public:
121-
ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
122-
StringRef FS, const TargetOptions &Options,
123-
Optional<Reloc::Model> RM, CodeModel::Model CM,
124-
CodeGenOpt::Level OL);
125-
};
126-
127-
/// Thumb big endian target machine.
128-
///
129-
class ThumbBETargetMachine : public ThumbTargetMachine {
130-
void anchor() override;
131-
132-
public:
133-
ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
134-
StringRef FS, const TargetOptions &Options,
135-
Optional<Reloc::Model> RM, CodeModel::Model CM,
136-
CodeGenOpt::Level OL);
137-
};
138-
13985
} // end namespace llvm
14086

14187
#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H

‎llvm/lib/Target/ARM/ARMTargetObjectFile.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ using namespace dwarf;
3030

3131
void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
3232
const TargetMachine &TM) {
33-
const ARMTargetMachine &ARM_TM = static_cast<const ARMTargetMachine &>(TM);
34-
bool isAAPCS_ABI = ARM_TM.TargetABI == ARMTargetMachine::ARMABI::ARM_ABI_AAPCS;
33+
const ARMBaseTargetMachine &ARM_TM = static_cast<const ARMBaseTargetMachine &>(TM);
34+
bool isAAPCS_ABI = ARM_TM.TargetABI == ARMBaseTargetMachine::ARMABI::ARM_ABI_AAPCS;
3535
genExecuteOnly = ARM_TM.getSubtargetImpl()->genExecuteOnly();
3636

3737
TargetLoweringObjectFileELF::Initialize(Ctx, TM);

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