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topperctopperc
committedApr 18, 2017
[APInt] Use lshrInPlace to replace lshr where possible
This patch uses lshrInPlace to replace code where the object that lshr is called on is being overwritten with the result. This adds an lshrInPlace(const APInt &) version as well. Differential Revision: https://reviews.llvm.org/D32155 llvm-svn: 300566
1 parent ec9deb7 commit fc947bc

18 files changed

+68
-56
lines changed
 

‎llvm/include/llvm/ADT/APInt.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -914,7 +914,14 @@ class LLVM_NODISCARD APInt {
914914
/// \brief Logical right-shift function.
915915
///
916916
/// Logical right-shift this APInt by shiftAmt.
917-
APInt lshr(const APInt &shiftAmt) const;
917+
APInt lshr(const APInt &ShiftAmt) const {
918+
APInt R(*this);
919+
R.lshrInPlace(ShiftAmt);
920+
return R;
921+
}
922+
923+
/// Logical right-shift this APInt by ShiftAmt in place.
924+
void lshrInPlace(const APInt &ShiftAmt);
918925

919926
/// \brief Left-shift function.
920927
///

‎llvm/lib/Analysis/ScalarEvolution.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1093,7 +1093,7 @@ static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K,
10931093
APInt Mult(W, i);
10941094
unsigned TwoFactors = Mult.countTrailingZeros();
10951095
T += TwoFactors;
1096-
Mult = Mult.lshr(TwoFactors);
1096+
Mult.lshrInPlace(TwoFactors);
10971097
OddFactorial *= Mult;
10981098
}
10991099

‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -661,8 +661,10 @@ static void computeKnownBitsFromAssume(const Value *V, APInt &KnownZero,
661661
computeKnownBits(A, RHSKnownZero, RHSKnownOne, Depth+1, Query(Q, I));
662662
// For those bits in RHS that are known, we can propagate them to known
663663
// bits in V shifted to the right by C.
664-
KnownZero |= RHSKnownZero.lshr(C->getZExtValue());
665-
KnownOne |= RHSKnownOne.lshr(C->getZExtValue());
664+
RHSKnownZero.lshrInPlace(C->getZExtValue());
665+
KnownZero |= RHSKnownZero;
666+
RHSKnownOne.lshrInPlace(C->getZExtValue());
667+
KnownOne |= RHSKnownOne;
666668
// assume(~(v << c) = a)
667669
} else if (match(Arg, m_c_ICmp(Pred, m_Not(m_Shl(m_V, m_ConstantInt(C))),
668670
m_Value(A))) &&
@@ -672,8 +674,10 @@ static void computeKnownBitsFromAssume(const Value *V, APInt &KnownZero,
672674
computeKnownBits(A, RHSKnownZero, RHSKnownOne, Depth+1, Query(Q, I));
673675
// For those bits in RHS that are known, we can propagate them inverted
674676
// to known bits in V shifted to the right by C.
675-
KnownZero |= RHSKnownOne.lshr(C->getZExtValue());
676-
KnownOne |= RHSKnownZero.lshr(C->getZExtValue());
677+
RHSKnownOne.lshrInPlace(C->getZExtValue());
678+
KnownZero |= RHSKnownOne;
679+
RHSKnownZero.lshrInPlace(C->getZExtValue());
680+
KnownOne |= RHSKnownZero;
677681
// assume(v >> c = a)
678682
} else if (match(Arg,
679683
m_c_ICmp(Pred, m_CombineOr(m_LShr(m_V, m_ConstantInt(C)),
@@ -1111,10 +1115,11 @@ static void computeKnownBitsFromOperator(const Operator *I, APInt &KnownZero,
11111115
}
11121116
case Instruction::LShr: {
11131117
// (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
1114-
auto KZF = [BitWidth](const APInt &KnownZero, unsigned ShiftAmt) {
1115-
return KnownZero.lshr(ShiftAmt) |
1116-
// High bits known zero.
1117-
APInt::getHighBitsSet(BitWidth, ShiftAmt);
1118+
auto KZF = [](const APInt &KnownZero, unsigned ShiftAmt) {
1119+
APInt KZResult = KnownZero.lshr(ShiftAmt);
1120+
// High bits known zero.
1121+
KZResult.setHighBits(ShiftAmt);
1122+
return KZResult;
11181123
};
11191124

11201125
auto KOF = [](const APInt &KnownOne, unsigned ShiftAmt) {

‎llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2246,7 +2246,7 @@ static void emitGlobalConstantLargeInt(const ConstantInt *CI, AsmPrinter &AP) {
22462246
// chu[nk1 chu][nk2 chu] ... [nkN-1 chunkN]
22472247
ExtraBits = Realigned.getRawData()[0] &
22482248
(((uint64_t)-1) >> (64 - ExtraBitsSize));
2249-
Realigned = Realigned.lshr(ExtraBitsSize);
2249+
Realigned.lshrInPlace(ExtraBitsSize);
22502250
} else
22512251
ExtraBits = Realigned.getRawData()[BitWidth / 64];
22522252
}

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5065,16 +5065,14 @@ bool CodeGenPrepare::optimizeLoadExt(LoadInst *Load) {
50655065
if (!ShlC)
50665066
return false;
50675067
uint64_t ShiftAmt = ShlC->getLimitedValue(BitWidth - 1);
5068-
auto ShlDemandBits = APInt::getAllOnesValue(BitWidth).lshr(ShiftAmt);
5069-
DemandBits |= ShlDemandBits;
5068+
DemandBits.setLowBits(BitWidth - ShiftAmt);
50705069
break;
50715070
}
50725071

50735072
case llvm::Instruction::Trunc: {
50745073
EVT TruncVT = TLI->getValueType(*DL, I->getType());
50755074
unsigned TruncBitWidth = TruncVT.getSizeInBits();
5076-
auto TruncBits = APInt::getAllOnesValue(TruncBitWidth).zext(BitWidth);
5077-
DemandBits |= TruncBits;
5075+
DemandBits.setLowBits(TruncBitWidth);
50785076
break;
50795077
}
50805078

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5350,7 +5350,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
53505350
Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
53515351
DAG.getConstant(c2 - c1, DL, N1.getValueType()));
53525352
} else {
5353-
Mask = Mask.lshr(c1 - c2);
5353+
Mask.lshrInPlace(c1 - c2);
53545354
SDLoc DL(N);
53555355
Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
53565356
DAG.getConstant(c1 - c2, DL, N1.getValueType()));
@@ -5660,7 +5660,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
56605660
DAG.getConstant(ShiftAmt, DL0,
56615661
getShiftAmountTy(SmallVT)));
56625662
AddToWorklist(SmallShift.getNode());
5663-
APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
5663+
APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt);
56645664
SDLoc DL(N);
56655665
return DAG.getNode(ISD::AND, DL, VT,
56665666
DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
@@ -8687,7 +8687,7 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
86878687
for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
86888688
APInt ThisVal = OpVal.trunc(DstBitSize);
86898689
Ops.push_back(DAG.getConstant(ThisVal, DL, DstEltVT));
8690-
OpVal = OpVal.lshr(DstBitSize);
8690+
OpVal.lshrInPlace(DstBitSize);
86918691
}
86928692

86938693
// For big endian targets, swap the order of the pieces of each element.
@@ -15143,9 +15143,9 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
1514315143

1514415144
// Extract the sub element from the constant bit mask.
1514515145
if (DAG.getDataLayout().isBigEndian()) {
15146-
Bits = Bits.lshr((Split - SubIdx - 1) * NumSubBits);
15146+
Bits.lshrInPlace((Split - SubIdx - 1) * NumSubBits);
1514715147
} else {
15148-
Bits = Bits.lshr(SubIdx * NumSubBits);
15148+
Bits.lshrInPlace(SubIdx * NumSubBits);
1514915149
}
1515015150

1515115151
if (Split > 1)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2330,8 +2330,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
23302330
if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
23312331
computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
23322332
Depth + 1);
2333-
KnownZero = KnownZero.lshr(*ShAmt);
2334-
KnownOne = KnownOne.lshr(*ShAmt);
2333+
KnownZero.lshrInPlace(*ShAmt);
2334+
KnownOne.lshrInPlace(*ShAmt);
23352335
// High bits are known zero.
23362336
KnownZero.setHighBits(ShAmt->getZExtValue());
23372337
}
@@ -2340,12 +2340,12 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
23402340
if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
23412341
computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
23422342
Depth + 1);
2343-
KnownZero = KnownZero.lshr(*ShAmt);
2344-
KnownOne = KnownOne.lshr(*ShAmt);
2343+
KnownZero.lshrInPlace(*ShAmt);
2344+
KnownOne.lshrInPlace(*ShAmt);
23452345
// If we know the value of the sign bit, then we know it is copied across
23462346
// the high bits by the shift amount.
23472347
APInt SignBit = APInt::getSignBit(BitWidth);
2348-
SignBit = SignBit.lshr(*ShAmt); // Adjust to where it is now in the mask.
2348+
SignBit.lshrInPlace(*ShAmt); // Adjust to where it is now in the mask.
23492349
if (KnownZero.intersects(SignBit)) {
23502350
KnownZero.setHighBits(ShAmt->getZExtValue());// New bits are known zero.
23512351
} else if (KnownOne.intersects(SignBit)) {

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -929,8 +929,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
929929
KnownZero, KnownOne, TLO, Depth+1))
930930
return true;
931931
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
932-
KnownZero = KnownZero.lshr(ShAmt);
933-
KnownOne = KnownOne.lshr(ShAmt);
932+
KnownZero.lshrInPlace(ShAmt);
933+
KnownOne.lshrInPlace(ShAmt);
934934

935935
KnownZero.setHighBits(ShAmt); // High bits known zero.
936936
}
@@ -970,8 +970,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
970970
KnownZero, KnownOne, TLO, Depth+1))
971971
return true;
972972
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
973-
KnownZero = KnownZero.lshr(ShAmt);
974-
KnownOne = KnownOne.lshr(ShAmt);
973+
KnownZero.lshrInPlace(ShAmt);
974+
KnownOne.lshrInPlace(ShAmt);
975975

976976
// Handle the sign bit, adjusted to where it is now in the mask.
977977
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
@@ -1207,7 +1207,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
12071207

12081208
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
12091209
OperandBitWidth - BitWidth);
1210-
HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1210+
HighBits.lshrInPlace(ShAmt->getZExtValue());
1211+
HighBits = HighBits.trunc(BitWidth);
12111212

12121213
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
12131214
// None of the shifted in bits are needed. Add a truncate of the
@@ -2055,7 +2056,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
20552056
} else {
20562057
ShiftBits = C1.countTrailingZeros();
20572058
}
2058-
NewC = NewC.lshr(ShiftBits);
2059+
NewC.lshrInPlace(ShiftBits);
20592060
if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
20602061
isLegalICmpImmediate(NewC.getSExtValue())) {
20612062
auto &DL = DAG.getDataLayout();

‎llvm/lib/ExecutionEngine/Interpreter/Execution.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1580,7 +1580,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy,
15801580
GenericValue Elt;
15811581
Elt.IntVal = Elt.IntVal.zext(SrcBitSize);
15821582
Elt.IntVal = TempSrc.AggregateVal[i].IntVal;
1583-
Elt.IntVal = Elt.IntVal.lshr(ShiftAmt);
1583+
Elt.IntVal.lshrInPlace(ShiftAmt);
15841584
// it could be DstBitSize == SrcBitSize, so check it
15851585
if (DstBitSize < SrcBitSize)
15861586
Elt.IntVal = Elt.IntVal.trunc(DstBitSize);

‎llvm/lib/IR/ConstantFold.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -223,7 +223,7 @@ static Constant *ExtractConstantBytes(Constant *C, unsigned ByteStart,
223223
if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) {
224224
APInt V = CI->getValue();
225225
if (ByteStart)
226-
V = V.lshr(ByteStart*8);
226+
V.lshrInPlace(ByteStart*8);
227227
V = V.trunc(ByteSize*8);
228228
return ConstantInt::get(CI->getContext(), V);
229229
}

‎llvm/lib/Support/APFloat.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3442,7 +3442,7 @@ void IEEEFloat::toString(SmallVectorImpl<char> &Str, unsigned FormatPrecision,
34423442
// Ignore trailing binary zeros.
34433443
int trailingZeros = significand.countTrailingZeros();
34443444
exp += trailingZeros;
3445-
significand = significand.lshr(trailingZeros);
3445+
significand.lshrInPlace(trailingZeros);
34463446

34473447
// Change the exponent from 2^e to 10^e.
34483448
if (exp == 0) {

‎llvm/lib/Support/APInt.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1134,8 +1134,8 @@ APInt APInt::ashr(unsigned shiftAmt) const {
11341134

11351135
/// Logical right-shift this APInt by shiftAmt.
11361136
/// @brief Logical right-shift function.
1137-
APInt APInt::lshr(const APInt &shiftAmt) const {
1138-
return lshr((unsigned)shiftAmt.getLimitedValue(BitWidth));
1137+
void APInt::lshrInPlace(const APInt &shiftAmt) {
1138+
lshrInPlace((unsigned)shiftAmt.getLimitedValue(BitWidth));
11391139
}
11401140

11411141
/// Logical right-shift this APInt by shiftAmt.
@@ -1149,7 +1149,7 @@ void APInt::lshrInPlace(unsigned ShiftAmt) {
11491149
return;
11501150
}
11511151

1152-
return tcShiftRight(pVal, getNumWords(), ShiftAmt);
1152+
tcShiftRight(pVal, getNumWords(), ShiftAmt);
11531153
}
11541154

11551155
/// Left-shift this APInt by shiftAmt.
@@ -2145,7 +2145,7 @@ void APInt::toString(SmallVectorImpl<char> &Str, unsigned Radix,
21452145
while (Tmp != 0) {
21462146
unsigned Digit = unsigned(Tmp.getRawData()[0]) & MaskAmt;
21472147
Str.push_back(Digits[Digit]);
2148-
Tmp = Tmp.lshr(ShiftAmt);
2148+
Tmp.lshrInPlace(ShiftAmt);
21492149
}
21502150
} else {
21512151
APInt divisor(Radix == 10? 4 : 8, Radix);

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1865,7 +1865,7 @@ static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
18651865
OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
18661866
getUsefulBits(Op, OpUsefulBits, Depth + 1);
18671867
// The interesting part was at zero in the argument
1868-
OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1868+
OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
18691869
}
18701870

18711871
UsefulBits &= OpUsefulBits;
@@ -1894,13 +1894,13 @@ static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
18941894
uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
18951895
Mask = Mask.shl(ShiftAmt);
18961896
getUsefulBits(Op, Mask, Depth + 1);
1897-
Mask = Mask.lshr(ShiftAmt);
1897+
Mask.lshrInPlace(ShiftAmt);
18981898
} else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
18991899
// Shift Right
19001900
// We do not handle AArch64_AM::ASR, because the sign will change the
19011901
// number of useful bits
19021902
uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1903-
Mask = Mask.lshr(ShiftAmt);
1903+
Mask.lshrInPlace(ShiftAmt);
19041904
getUsefulBits(Op, Mask, Depth + 1);
19051905
Mask = Mask.shl(ShiftAmt);
19061906
} else
@@ -1954,7 +1954,7 @@ static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
19541954
if (Op.getOperand(1) == Orig) {
19551955
// Copy the bits from the result to the zero bits.
19561956
Mask = ResultUsefulBits & OpUsefulBits;
1957-
Mask = Mask.lshr(LSB);
1957+
Mask.lshrInPlace(LSB);
19581958
}
19591959

19601960
if (Op.getOperand(0) == Orig)

‎llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2004,7 +2004,7 @@ void NVPTXAsmPrinter::bufferAggregateConstant(const Constant *CPV,
20042004
for (unsigned I = 0, E = DL.getTypeAllocSize(CPV->getType()); I < E; ++I) {
20052005
uint8_t Byte = Val.getLoBits(8).getZExtValue();
20062006
aggBuffer->addBytes(&Byte, 1, 1);
2007-
Val = Val.lshr(8);
2007+
Val.lshrInPlace(8);
20082008
}
20092009
return;
20102010
}

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8327,13 +8327,13 @@ static APInt computeZeroableShuffleElements(ArrayRef<int> Mask,
83278327
Zeroable.setBit(i);
83288328
else if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
83298329
APInt Val = Cst->getAPIntValue();
8330-
Val = Val.lshr((M % Scale) * ScalarSizeInBits);
8330+
Val.lshrInPlace((M % Scale) * ScalarSizeInBits);
83318331
Val = Val.getLoBits(ScalarSizeInBits);
83328332
if (Val == 0)
83338333
Zeroable.setBit(i);
83348334
} else if (ConstantFPSDNode *Cst = dyn_cast<ConstantFPSDNode>(Op)) {
83358335
APInt Val = Cst->getValueAPF().bitcastToAPInt();
8336-
Val = Val.lshr((M % Scale) * ScalarSizeInBits);
8336+
Val.lshrInPlace((M % Scale) * ScalarSizeInBits);
83378337
Val = Val.getLoBits(ScalarSizeInBits);
83388338
if (Val == 0)
83398339
Zeroable.setBit(i);
@@ -26722,8 +26722,8 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
2672226722
// Low bits are known zero.
2672326723
KnownZero.setLowBits(ShAmt);
2672426724
} else {
26725-
KnownZero = KnownZero.lshr(ShAmt);
26726-
KnownOne = KnownOne.lshr(ShAmt);
26725+
KnownZero.lshrInPlace(ShAmt);
26726+
KnownOne.lshrInPlace(ShAmt);
2672726727
// High bits are known zero.
2672826728
KnownZero.setHighBits(ShAmt);
2672926729
}
@@ -31269,7 +31269,7 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
3126931269
else if (X86ISD::VSRAI == Opcode)
3127031270
Elt = Elt.ashr(ShiftImm);
3127131271
else
31272-
Elt = Elt.lshr(ShiftImm);
31272+
Elt.lshrInPlace(ShiftImm);
3127331273
}
3127431274
return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N));
3127531275
}

‎llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -839,7 +839,8 @@ static Value *simplifyX86extrq(IntrinsicInst &II, Value *Op0,
839839
// Length bits.
840840
if (CI0) {
841841
APInt Elt = CI0->getValue();
842-
Elt = Elt.lshr(Index).zextOrTrunc(Length);
842+
Elt.lshrInPlace(Index);
843+
Elt = Elt.zextOrTrunc(Length);
843844
return LowConstantHighUndef(Elt.getZExtValue());
844845
}
845846

@@ -1036,7 +1037,7 @@ static Value *simplifyX86vpermilvar(const IntrinsicInst &II,
10361037
// The PD variants uses bit 1 to select per-lane element index, so
10371038
// shift down to convert to generic shuffle mask index.
10381039
if (IsPD)
1039-
Index = Index.lshr(1);
1040+
Index.lshrInPlace(1);
10401041

10411042
// The _256 variants are a bit trickier since the mask bits always index
10421043
// into the corresponding 128 half. In order to convert to a generic

‎llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -370,7 +370,7 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
370370
MaskV <<= Op1C->getZExtValue();
371371
else {
372372
assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
373-
MaskV = MaskV.lshr(Op1C->getZExtValue());
373+
MaskV.lshrInPlace(Op1C->getZExtValue());
374374
}
375375

376376
// shift1 & 0x00FF

‎llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -546,8 +546,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
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Depth + 1))
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return I;
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assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
549-
KnownZero = KnownZero.lshr(ShiftAmt);
550-
KnownOne = KnownOne.lshr(ShiftAmt);
549+
KnownZero.lshrInPlace(ShiftAmt);
550+
KnownOne.lshrInPlace(ShiftAmt);
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if (ShiftAmt)
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KnownZero.setHighBits(ShiftAmt); // high bits known zero.
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}
@@ -590,13 +590,13 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
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assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
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// Compute the new bits that are at the top now.
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APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
593-
KnownZero = KnownZero.lshr(ShiftAmt);
594-
KnownOne = KnownOne.lshr(ShiftAmt);
593+
KnownZero.lshrInPlace(ShiftAmt);
594+
KnownOne.lshrInPlace(ShiftAmt);
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// Handle the sign bits.
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APInt SignBit(APInt::getSignBit(BitWidth));
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// Adjust to where it is now in the mask.
599-
SignBit = SignBit.lshr(ShiftAmt);
599+
SignBit.lshrInPlace(ShiftAmt);
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601601
// If the input sign bit is known to be zero, or if none of the top bits
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// are demanded, turn this into an unsigned shift right.

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