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committedApr 14, 2017
Fix for PR#30562: Selection DAG error: Detected cycle in SelectionDAG.
Patch by Dinar Temirbulatov llvm-svn: 300314
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+27
-2
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+27
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‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

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Original file line numberDiff line numberDiff line change
@@ -1192,8 +1192,11 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
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// If the index is dependent on the store we will introduce a cycle when
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// creating the load (the load uses the index, and by replacing the chain
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// we will make the index dependent on the load).
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if (SDNode::hasPredecessorHelper(ST, Visited, Worklist))
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// we will make the index dependent on the load). Also, the store might be
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// dependent on the extractelement and introduce a cycle when creating
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// the load.
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if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
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ST->hasPredecessor(Op.getNode()))
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continue;
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StackPtr = ST->getBasePtr();

‎llvm/test/CodeGen/X86/pr30562.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i32 @foo(i64* nocapture %perm, i32 %n) {
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entry:
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br label %body
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body:
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; CHECK-LABEL: foo:
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; CHECK: pslldq $8, %xmm0
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%vec.ind = phi <2 x i64> [ <i64 0, i64 1>, %entry ], [ <i64 2, i64 3>, %body ]
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%l13 = extractelement <2 x i64> %vec.ind, i32 %n
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%l14 = getelementptr inbounds i64, i64* %perm, i64 %l13
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%l15 = bitcast i64* %l14 to <2 x i64>*
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store <2 x i64> %vec.ind, <2 x i64>* %l15, align 8
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%niter.ncmp.3 = icmp eq i64 %l13, 0
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br i1 %niter.ncmp.3, label %exit, label %body
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exit:
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ret i32 %n
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}
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