Skip to content

Commit 75bdc76

Browse files
author
Volkan Keles
committedMar 21, 2017
[GlobalISel] Translate shufflevector
Reviewers: qcolombet, aditya_nandakumar, t.p.northover, javed.absar, ab, dsanders Reviewed By: javed.absar Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30962 llvm-svn: 298347
·
llvmorg-21-initllvmorg-5.0.0-rc1
1 parent 9353e2d commit 75bdc76

File tree

6 files changed

+211
-4
lines changed

6 files changed

+211
-4
lines changed
 

‎llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

+2-3
Original file line numberDiff line numberDiff line change
@@ -299,6 +299,8 @@ class IRTranslator : public MachineFunctionPass {
299299

300300
bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
301301

302+
bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
303+
302304
// Stubs to keep the compiler happy while we implement the rest of the
303305
// translation.
304306
bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
@@ -337,9 +339,6 @@ class IRTranslator : public MachineFunctionPass {
337339
bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
338340
return false;
339341
}
340-
bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder) {
341-
return false;
342-
}
343342

344343
/// @}
345344

‎llvm/include/llvm/Target/GenericOpcodes.td

+7
Original file line numberDiff line numberDiff line change
@@ -537,4 +537,11 @@ def G_EXTRACT_VECTOR_ELT : Instruction {
537537
let hasSideEffects = 0;
538538
}
539539

540+
// Generic shufflevector.
541+
def G_SHUFFLE_VECTOR: Instruction {
542+
let OutOperandList = (outs type0:$dst);
543+
let InOperandList = (ins type1:$v1, type1:$v2, type2:$mask);
544+
let hasSideEffects = 0;
545+
}
546+
540547
// TODO: Add the other generic opcodes.

‎llvm/include/llvm/Target/TargetOpcodes.def

+4-1
Original file line numberDiff line numberDiff line change
@@ -401,12 +401,15 @@ HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
401401
/// Generic extractelement.
402402
HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
403403

404+
/// Generic shufflevector.
405+
HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
406+
404407
// TODO: Add more generic opcodes as we move along.
405408

406409
/// Marker for the end of the generic opcode.
407410
/// This is used to check if an opcode is in the range of the
408411
/// generic opcodes.
409-
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_EXTRACT_VECTOR_ELT)
412+
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_SHUFFLE_VECTOR)
410413

411414
/// BUILTIN_OP_END - This must be the last enum value in this list.
412415
/// The target-specific post-isel opcode values start here.

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

+10
Original file line numberDiff line numberDiff line change
@@ -1005,6 +1005,16 @@ bool IRTranslator::translateExtractElement(const User &U,
10051005
return true;
10061006
}
10071007

1008+
bool IRTranslator::translateShuffleVector(const User &U,
1009+
MachineIRBuilder &MIRBuilder) {
1010+
MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1011+
.addDef(getOrCreateVReg(U))
1012+
.addUse(getOrCreateVReg(*U.getOperand(0)))
1013+
.addUse(getOrCreateVReg(*U.getOperand(1)))
1014+
.addUse(getOrCreateVReg(*U.getOperand(2)));
1015+
return true;
1016+
}
1017+
10081018
bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
10091019
const PHINode &PI = cast<PHINode>(U);
10101020
auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

+108
Original file line numberDiff line numberDiff line change
@@ -1411,3 +1411,111 @@ define float @test_different_call_conv_target(float %x) {
14111411
%res = call ghccc float @different_call_conv_target(float %x)
14121412
ret float %res
14131413
}
1414+
1415+
define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
1416+
; CHECK-LABEL: name: test_shufflevector_s32_v2s32
1417+
; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
1418+
; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
1419+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1420+
; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
1421+
; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
1422+
; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1423+
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
1424+
%res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
1425+
ret <2 x i32> %res
1426+
}
1427+
1428+
define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
1429+
; CHECK-LABEL: name: test_shufflevector_v2s32_s32
1430+
; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1431+
; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
1432+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1433+
; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
1434+
; CHECK: %w0 = COPY [[RES]](s32)
1435+
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
1436+
%res = extractelement <1 x i32> %vec, i32 0
1437+
ret i32 %res
1438+
}
1439+
1440+
define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
1441+
; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
1442+
; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1443+
; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
1444+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1445+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1446+
; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
1447+
; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1448+
; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1449+
%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
1450+
ret <2 x i32> %res
1451+
}
1452+
1453+
define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
1454+
; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
1455+
; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
1456+
; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
1457+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1458+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1459+
; CHECK: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
1460+
; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
1461+
; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
1462+
%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
1463+
%res = extractelement <3 x i32> %vec, i32 0
1464+
ret i32 %res
1465+
}
1466+
1467+
define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
1468+
; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
1469+
; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0
1470+
; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1
1471+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1472+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1473+
; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1474+
; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1475+
; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
1476+
; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
1477+
; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
1478+
%res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1479+
ret <4 x i32> %res
1480+
}
1481+
1482+
define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
1483+
; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
1484+
; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
1485+
; CHECK: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
1486+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1487+
; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1488+
; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
1489+
; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1490+
; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1491+
%res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
1492+
ret <2 x i32> %res
1493+
}
1494+
1495+
1496+
define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
1497+
; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
1498+
; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0
1499+
; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1
1500+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
1501+
; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8
1502+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
1503+
; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9
1504+
; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
1505+
; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10
1506+
; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
1507+
; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11
1508+
; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
1509+
; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12
1510+
; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5
1511+
; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13
1512+
; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6
1513+
; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14
1514+
; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
1515+
; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
1516+
; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
1517+
; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
1518+
; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
1519+
%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
1520+
ret <16 x i8> %res
1521+
}

‎llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

+80
Original file line numberDiff line numberDiff line change
@@ -543,3 +543,83 @@ entry:
543543
%r = notail call arm_aapcscc float @different_call_conv_target(float %x)
544544
ret float %r
545545
}
546+
547+
define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
548+
; CHECK-LABEL: name: test_shufflevector_s32_v2s32
549+
; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0
550+
; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
551+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
552+
; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
553+
; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
554+
; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
555+
%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
556+
%shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
557+
%res = extractelement <2 x i32> %shuffle, i32 0
558+
ret i32 %res
559+
}
560+
561+
define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
562+
; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
563+
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
564+
; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
565+
; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
566+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
567+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
568+
; CHECK: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
569+
; CHECK: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
570+
; CHECK: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
571+
; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
572+
; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
573+
%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
574+
%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
575+
%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
576+
%res = extractelement <3 x i32> %shuffle, i32 0
577+
ret i32 %res
578+
}
579+
580+
581+
define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
582+
; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
583+
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
584+
; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
585+
; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
586+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
587+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
588+
; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32)
589+
; CHECK: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
590+
; CHECK: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
591+
; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<4 x s32>)
592+
; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>)
593+
%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
594+
%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
595+
%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <4 x i32> zeroinitializer
596+
%res = extractelement <4 x i32> %shuffle, i32 0
597+
ret i32 %res
598+
}
599+
600+
define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
601+
; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
602+
; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
603+
; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
604+
; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %r2
605+
; CHECK: [[ARG4:%[0-9]+]](s32) = COPY %r3
606+
; CHECK: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
607+
; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
608+
; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
609+
; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
610+
; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
611+
; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
612+
; CHECK: [[V1:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
613+
; CHECK: [[V2:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
614+
; CHECK: [[V3:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)
615+
; CHECK: [[V4:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)
616+
; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
617+
; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
618+
%v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0
619+
%v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1
620+
%v3 = insertelement <4 x i32> %v2, i32 %arg3, i32 2
621+
%v4 = insertelement <4 x i32> %v3, i32 %arg4, i32 3
622+
%shuffle = shufflevector <4 x i32> %v4, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
623+
%res = extractelement <2 x i32> %shuffle, i32 0
624+
ret i32 %res
625+
}

0 commit comments

Comments
 (0)
Please sign in to comment.