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rotaterightrotateright
committedFeb 24, 2017
[DAGCombiner] add missing folds for scalar select of {-1,0,1}
The motivation for filling out these select-of-constants cases goes back to D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to: https://reviews.llvm.org/rL75531 https://reviews.llvm.org/rL159230 The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today: https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151 As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization: 1. Have DAGCombiner convert any select of constants into ext/add/not ops. 2 Have InstCombine canonicalize in the other direction (create more selects). Differential Revision: https://reviews.llvm.org/D30180 llvm-svn: 296137
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5599,15 +5599,39 @@ SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
55995599
if (!isa<ConstantSDNode>(N1) || !isa<ConstantSDNode>(N2))
56005600
return SDValue();
56015601

5602-
// TODO: We should handle other cases of selecting between {-1,0,1} here.
5603-
if (CondVT == MVT::i1) {
5602+
// Only do this before legalization to avoid conflicting with target-specific
5603+
// transforms in the other direction (create a select from a zext/sext). There
5604+
// is also a target-independent combine here in DAGCombiner in the other
5605+
// direction for (select Cond, -1, 0) when the condition is not i1.
5606+
// TODO: This could be generalized for any 2 constants that differ by 1:
5607+
// add ({s/z}ext Cond), C
5608+
if (CondVT == MVT::i1 && !LegalOperations) {
56045609
if (isNullConstant(N1) && isOneConstant(N2)) {
56055610
// select Cond, 0, 1 --> zext (!Cond)
56065611
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
56075612
if (VT != MVT::i1)
56085613
NotCond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotCond);
56095614
return NotCond;
56105615
}
5616+
if (isNullConstant(N1) && isAllOnesConstant(N2)) {
5617+
// select Cond, 0, -1 --> sext (!Cond)
5618+
SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
5619+
if (VT != MVT::i1)
5620+
NotCond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NotCond);
5621+
return NotCond;
5622+
}
5623+
if (isOneConstant(N1) && isNullConstant(N2)) {
5624+
// select Cond, 1, 0 --> zext (Cond)
5625+
if (VT != MVT::i1)
5626+
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
5627+
return Cond;
5628+
}
5629+
if (isAllOnesConstant(N1) && isNullConstant(N2)) {
5630+
// select Cond, -1, 0 --> sext (Cond)
5631+
if (VT != MVT::i1)
5632+
Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
5633+
return Cond;
5634+
}
56115635
return SDValue();
56125636
}
56135637

@@ -6766,7 +6790,12 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
67666790

67676791
if (!VT.isVector()) {
67686792
EVT SetCCVT = getSetCCResultType(N00VT);
6769-
if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT)) {
6793+
// Don't do this transform for i1 because there's a select transform
6794+
// that would reverse it.
6795+
// TODO: We should not do this transform at all without a target hook
6796+
// because a sext is likely cheaper than a select?
6797+
if (SetCCVT.getScalarSizeInBits() != 1 &&
6798+
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) {
67706799
SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC);
67716800
return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero);
67726801
}

‎llvm/test/CodeGen/AMDGPU/trunc.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,7 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64
5656
}
5757

5858
; GCN-LABEL: {{^}}trunc_i32_to_i1:
59-
; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
60-
; GCN: v_cmp_eq_u32
59+
; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
6160
define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
6261
%a = load i32, i32 addrspace(1)* %ptr, align 4
6362
%trunc = trunc i32 %a to i1
@@ -67,8 +66,7 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
6766
}
6867

6968
; GCN-LABEL: {{^}}trunc_i8_to_i1:
70-
; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
71-
; GCN: v_cmp_eq_u32
69+
; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
7270
define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
7371
%a = load i8, i8 addrspace(1)* %ptr, align 4
7472
%trunc = trunc i8 %a to i1
@@ -78,8 +76,7 @@ define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
7876
}
7977

8078
; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
81-
; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
82-
; GCN: v_cmp_eq_u32
79+
; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
8380
define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
8481
%trunc = trunc i16 %a to i1
8582
%result = select i1 %trunc, i16 1, i16 0
@@ -88,8 +85,7 @@ define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
8885
}
8986

9087
; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
91-
; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
92-
; GCN: v_cmp_eq_u32
88+
; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
9389
define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
9490
%trunc = trunc i32 %a to i1
9591
%result = select i1 %trunc, i32 1, i32 0

‎llvm/test/CodeGen/ARM/select_const.ll

Lines changed: 11 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,7 @@ define i32 @select_0_or_1_signext(i1 signext %cond) {
4040
define i32 @select_1_or_0(i1 %cond) {
4141
; CHECK-LABEL: select_1_or_0:
4242
; CHECK: @ BB#0:
43-
; CHECK-NEXT: ands r0, r0, #1
44-
; CHECK-NEXT: movne r0, #1
43+
; CHECK-NEXT: and r0, r0, #1
4544
; CHECK-NEXT: mov pc, lr
4645
%sel = select i1 %cond, i32 1, i32 0
4746
ret i32 %sel
@@ -50,8 +49,6 @@ define i32 @select_1_or_0(i1 %cond) {
5049
define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
5150
; CHECK-LABEL: select_1_or_0_zeroext:
5251
; CHECK: @ BB#0:
53-
; CHECK-NEXT: cmp r0, #0
54-
; CHECK-NEXT: movne r0, #1
5552
; CHECK-NEXT: mov pc, lr
5653
%sel = select i1 %cond, i32 1, i32 0
5754
ret i32 %sel
@@ -60,8 +57,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
6057
define i32 @select_1_or_0_signext(i1 signext %cond) {
6158
; CHECK-LABEL: select_1_or_0_signext:
6259
; CHECK: @ BB#0:
63-
; CHECK-NEXT: ands r0, r0, #1
64-
; CHECK-NEXT: movne r0, #1
60+
; CHECK-NEXT: and r0, r0, #1
6561
; CHECK-NEXT: mov pc, lr
6662
%sel = select i1 %cond, i32 1, i32 0
6763
ret i32 %sel
@@ -72,10 +68,9 @@ define i32 @select_1_or_0_signext(i1 signext %cond) {
7268
define i32 @select_0_or_neg1(i1 %cond) {
7369
; CHECK-LABEL: select_0_or_neg1:
7470
; CHECK: @ BB#0:
75-
; CHECK-NEXT: mvn r1, #0
76-
; CHECK-NEXT: tst r0, #1
77-
; CHECK-NEXT: movne r1, #0
78-
; CHECK-NEXT: mov r0, r1
71+
; CHECK-NEXT: mov r1, #1
72+
; CHECK-NEXT: bic r0, r1, r0
73+
; CHECK-NEXT: rsb r0, r0, #0
7974
; CHECK-NEXT: mov pc, lr
8075
%sel = select i1 %cond, i32 0, i32 -1
8176
ret i32 %sel
@@ -84,10 +79,8 @@ define i32 @select_0_or_neg1(i1 %cond) {
8479
define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
8580
; CHECK-LABEL: select_0_or_neg1_zeroext:
8681
; CHECK: @ BB#0:
87-
; CHECK-NEXT: mvn r1, #0
88-
; CHECK-NEXT: cmp r0, #0
89-
; CHECK-NEXT: movne r1, #0
90-
; CHECK-NEXT: mov r0, r1
82+
; CHECK-NEXT: eor r0, r0, #1
83+
; CHECK-NEXT: rsb r0, r0, #0
9184
; CHECK-NEXT: mov pc, lr
9285
%sel = select i1 %cond, i32 0, i32 -1
9386
ret i32 %sel
@@ -96,10 +89,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
9689
define i32 @select_0_or_neg1_signext(i1 signext %cond) {
9790
; CHECK-LABEL: select_0_or_neg1_signext:
9891
; CHECK: @ BB#0:
99-
; CHECK-NEXT: mvn r1, #0
100-
; CHECK-NEXT: tst r0, #1
101-
; CHECK-NEXT: movne r1, #0
102-
; CHECK-NEXT: mov r0, r1
92+
; CHECK-NEXT: mvn r0, r0
10393
; CHECK-NEXT: mov pc, lr
10494
%sel = select i1 %cond, i32 0, i32 -1
10595
ret i32 %sel
@@ -110,8 +100,8 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) {
110100
define i32 @select_neg1_or_0(i1 %cond) {
111101
; CHECK-LABEL: select_neg1_or_0:
112102
; CHECK: @ BB#0:
113-
; CHECK-NEXT: ands r0, r0, #1
114-
; CHECK-NEXT: mvnne r0, #0
103+
; CHECK-NEXT: and r0, r0, #1
104+
; CHECK-NEXT: rsb r0, r0, #0
115105
; CHECK-NEXT: mov pc, lr
116106
%sel = select i1 %cond, i32 -1, i32 0
117107
ret i32 %sel
@@ -120,8 +110,7 @@ define i32 @select_neg1_or_0(i1 %cond) {
120110
define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
121111
; CHECK-LABEL: select_neg1_or_0_zeroext:
122112
; CHECK: @ BB#0:
123-
; CHECK-NEXT: cmp r0, #0
124-
; CHECK-NEXT: mvnne r0, #0
113+
; CHECK-NEXT: rsb r0, r0, #0
125114
; CHECK-NEXT: mov pc, lr
126115
%sel = select i1 %cond, i32 -1, i32 0
127116
ret i32 %sel
@@ -130,8 +119,6 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
130119
define i32 @select_neg1_or_0_signext(i1 signext %cond) {
131120
; CHECK-LABEL: select_neg1_or_0_signext:
132121
; CHECK: @ BB#0:
133-
; CHECK-NEXT: ands r0, r0, #1
134-
; CHECK-NEXT: mvnne r0, #0
135122
; CHECK-NEXT: mov pc, lr
136123
%sel = select i1 %cond, i32 -1, i32 0
137124
ret i32 %sel

‎llvm/test/CodeGen/Hexagon/adde.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,12 @@
11
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
22

3-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1)
4-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0)
53
; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
4+
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1)
65
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
76
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
8-
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
9-
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
10-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})
7+
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},#1,#0)
8+
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,r{{[0-9]+}})
9+
; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
1110
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
1211
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
1312
; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})

‎llvm/test/CodeGen/Hexagon/sube.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,11 @@
11
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
22

3-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0)
4-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1)
53
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
64
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
7-
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
8-
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
5+
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},#1,#0
6+
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
7+
; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,r{{[0-9]+}})
98
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
10-
; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})
119

1210
define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
1311
entry:

‎llvm/test/CodeGen/NVPTX/add-128bit.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ define void @foo(i64 %a, i64 %add, i128* %retptr) {
88
; CHECK: add.s64
99
; CHECK: setp.lt.u64
1010
; CHECK: setp.lt.u64
11-
; CHECK: selp.b64
11+
; CHECK: selp.u64
1212
; CHECK: selp.b64
1313
; CHECK: add.s64
1414
%t1 = sext i64 %a to i128

‎llvm/test/CodeGen/PowerPC/select_const.ll

Lines changed: 11 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -39,70 +39,27 @@ define i32 @select_0_or_1_signext(i1 signext %cond) {
3939
; select Cond, 1, 0 --> zext (Cond)
4040

4141
define i32 @select_1_or_0(i1 %cond) {
42-
; ISEL-LABEL: select_1_or_0:
43-
; ISEL: # BB#0:
44-
; ISEL-NEXT: andi. 3, 3, 1
45-
; ISEL-NEXT: li 4, 1
46-
; ISEL-NEXT: li 3, 0
47-
; ISEL-NEXT: isel 3, 4, 3, 1
48-
; ISEL-NEXT: blr
49-
;
50-
; NO_ISEL-LABEL: select_1_or_0:
51-
; NO_ISEL: # BB#0:
52-
; NO_ISEL-NEXT: andi. 3, 3, 1
53-
; NO_ISEL-NEXT: li 4, 1
54-
; NO_ISEL-NEXT: li 3, 0
55-
; NO_ISEL-NEXT: bc 12, 1, .LBB3_1
56-
; NO_ISEL-NEXT: blr
57-
; NO_ISEL-NEXT: .LBB3_1:
58-
; NO_ISEL-NEXT: addi 3, 4, 0
59-
; NO_ISEL-NEXT: blr
42+
; ALL-LABEL: select_1_or_0:
43+
; ALL: # BB#0:
44+
; ALL-NEXT: clrldi 3, 3, 63
45+
; ALL-NEXT: blr
6046
%sel = select i1 %cond, i32 1, i32 0
6147
ret i32 %sel
6248
}
6349

6450
define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
65-
; ISEL-LABEL: select_1_or_0_zeroext:
66-
; ISEL: # BB#0:
67-
; ISEL-NEXT: andi. 3, 3, 1
68-
; ISEL-NEXT: li 4, 1
69-
; ISEL-NEXT: li 3, 0
70-
; ISEL-NEXT: isel 3, 4, 3, 1
71-
; ISEL-NEXT: blr
72-
;
73-
; NO_ISEL-LABEL: select_1_or_0_zeroext:
74-
; NO_ISEL: # BB#0:
75-
; NO_ISEL-NEXT: andi. 3, 3, 1
76-
; NO_ISEL-NEXT: li 4, 1
77-
; NO_ISEL-NEXT: li 3, 0
78-
; NO_ISEL-NEXT: bc 12, 1, .LBB4_1
79-
; NO_ISEL-NEXT: blr
80-
; NO_ISEL-NEXT: .LBB4_1:
81-
; NO_ISEL-NEXT: addi 3, 4, 0
82-
; NO_ISEL-NEXT: blr
51+
; ALL-LABEL: select_1_or_0_zeroext:
52+
; ALL: # BB#0:
53+
; ALL-NEXT: blr
8354
%sel = select i1 %cond, i32 1, i32 0
8455
ret i32 %sel
8556
}
8657

8758
define i32 @select_1_or_0_signext(i1 signext %cond) {
88-
; ISEL-LABEL: select_1_or_0_signext:
89-
; ISEL: # BB#0:
90-
; ISEL-NEXT: andi. 3, 3, 1
91-
; ISEL-NEXT: li 4, 1
92-
; ISEL-NEXT: li 3, 0
93-
; ISEL-NEXT: isel 3, 4, 3, 1
94-
; ISEL-NEXT: blr
95-
;
96-
; NO_ISEL-LABEL: select_1_or_0_signext:
97-
; NO_ISEL: # BB#0:
98-
; NO_ISEL-NEXT: andi. 3, 3, 1
99-
; NO_ISEL-NEXT: li 4, 1
100-
; NO_ISEL-NEXT: li 3, 0
101-
; NO_ISEL-NEXT: bc 12, 1, .LBB5_1
102-
; NO_ISEL-NEXT: blr
103-
; NO_ISEL-NEXT: .LBB5_1:
104-
; NO_ISEL-NEXT: addi 3, 4, 0
105-
; NO_ISEL-NEXT: blr
59+
; ALL-LABEL: select_1_or_0_signext:
60+
; ALL: # BB#0:
61+
; ALL-NEXT: clrldi 3, 3, 63
62+
; ALL-NEXT: blr
10663
%sel = select i1 %cond, i32 1, i32 0
10764
ret i32 %sel
10865
}

‎llvm/test/CodeGen/X86/select_const.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -108,10 +108,9 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) {
108108
define i32 @select_neg1_or_0(i1 %cond) {
109109
; CHECK-LABEL: select_neg1_or_0:
110110
; CHECK: # BB#0:
111-
; CHECK-NEXT: xorl %ecx, %ecx
112-
; CHECK-NEXT: testb $1, %dil
113-
; CHECK-NEXT: movl $-1, %eax
114-
; CHECK-NEXT: cmovel %ecx, %eax
111+
; CHECK-NEXT: andl $1, %edi
112+
; CHECK-NEXT: negl %edi
113+
; CHECK-NEXT: movl %edi, %eax
115114
; CHECK-NEXT: retq
116115
%sel = select i1 %cond, i32 -1, i32 0
117116
ret i32 %sel
@@ -120,10 +119,8 @@ define i32 @select_neg1_or_0(i1 %cond) {
120119
define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
121120
; CHECK-LABEL: select_neg1_or_0_zeroext:
122121
; CHECK: # BB#0:
123-
; CHECK-NEXT: xorl %ecx, %ecx
124-
; CHECK-NEXT: testb %dil, %dil
125-
; CHECK-NEXT: movl $-1, %eax
126-
; CHECK-NEXT: cmovel %ecx, %eax
122+
; CHECK-NEXT: movzbl %dil, %eax
123+
; CHECK-NEXT: negl %eax
127124
; CHECK-NEXT: retq
128125
%sel = select i1 %cond, i32 -1, i32 0
129126
ret i32 %sel
@@ -132,10 +129,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
132129
define i32 @select_neg1_or_0_signext(i1 signext %cond) {
133130
; CHECK-LABEL: select_neg1_or_0_signext:
134131
; CHECK: # BB#0:
135-
; CHECK-NEXT: xorl %ecx, %ecx
136-
; CHECK-NEXT: testb $1, %dil
137-
; CHECK-NEXT: movl $-1, %eax
138-
; CHECK-NEXT: cmovel %ecx, %eax
132+
; CHECK-NEXT: movsbl %dil, %eax
139133
; CHECK-NEXT: retq
140134
%sel = select i1 %cond, i32 -1, i32 0
141135
ret i32 %sel

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