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committedDec 7, 2016
[X86][SSE] Remove AND -> VZEXT combine
This is now performed more generally by the target shuffle combine code. Already covered by tests that were originally added in D7666/rL229480 to support combineVectorZext (or VectorZextCombine as it was known then....). Differential Revision: https://reviews.llvm.org/D27510 llvm-svn: 288918
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

-92
Original file line numberDiff line numberDiff line change
@@ -29893,95 +29893,6 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
2989329893
}
2989429894
}
2989529895

29896-
static SDValue combineVectorZext(SDNode *N, SelectionDAG &DAG,
29897-
TargetLowering::DAGCombinerInfo &DCI,
29898-
const X86Subtarget &Subtarget) {
29899-
SDValue N0 = N->getOperand(0);
29900-
SDValue N1 = N->getOperand(1);
29901-
SDLoc DL(N);
29902-
29903-
// A vector zext_in_reg may be represented as a shuffle,
29904-
// feeding into a bitcast (this represents anyext) feeding into
29905-
// an and with a mask.
29906-
// We'd like to try to combine that into a shuffle with zero
29907-
// plus a bitcast, removing the and.
29908-
if (N0.getOpcode() != ISD::BITCAST ||
29909-
N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
29910-
return SDValue();
29911-
29912-
// The other side of the AND should be a splat of 2^C, where C
29913-
// is the number of bits in the source type.
29914-
N1 = peekThroughBitcasts(N1);
29915-
if (N1.getOpcode() != ISD::BUILD_VECTOR)
29916-
return SDValue();
29917-
BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
29918-
29919-
ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
29920-
EVT SrcType = Shuffle->getValueType(0);
29921-
29922-
// We expect a single-source shuffle
29923-
if (!Shuffle->getOperand(1)->isUndef())
29924-
return SDValue();
29925-
29926-
unsigned SrcSize = SrcType.getScalarSizeInBits();
29927-
unsigned NumElems = SrcType.getVectorNumElements();
29928-
29929-
APInt SplatValue, SplatUndef;
29930-
unsigned SplatBitSize;
29931-
bool HasAnyUndefs;
29932-
if (!Vector->isConstantSplat(SplatValue, SplatUndef,
29933-
SplatBitSize, HasAnyUndefs))
29934-
return SDValue();
29935-
29936-
unsigned ResSize = N1.getScalarValueSizeInBits();
29937-
// Make sure the splat matches the mask we expect
29938-
if (SplatBitSize > ResSize ||
29939-
(SplatValue + 1).exactLogBase2() != (int)SrcSize)
29940-
return SDValue();
29941-
29942-
// Make sure the input and output size make sense
29943-
if (SrcSize >= ResSize || ResSize % SrcSize)
29944-
return SDValue();
29945-
29946-
// We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
29947-
// The number of u's between each two values depends on the ratio between
29948-
// the source and dest type.
29949-
unsigned ZextRatio = ResSize / SrcSize;
29950-
bool IsZext = true;
29951-
for (unsigned i = 0; i != NumElems; ++i) {
29952-
if (i % ZextRatio) {
29953-
if (Shuffle->getMaskElt(i) > 0) {
29954-
// Expected undef
29955-
IsZext = false;
29956-
break;
29957-
}
29958-
} else {
29959-
if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
29960-
// Expected element number
29961-
IsZext = false;
29962-
break;
29963-
}
29964-
}
29965-
}
29966-
29967-
if (!IsZext)
29968-
return SDValue();
29969-
29970-
// Ok, perform the transformation - replace the shuffle with
29971-
// a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
29972-
// (instead of undef) where the k elements come from the zero vector.
29973-
SmallVector<int, 8> Mask;
29974-
for (unsigned i = 0; i != NumElems; ++i)
29975-
if (i % ZextRatio)
29976-
Mask.push_back(NumElems);
29977-
else
29978-
Mask.push_back(i / ZextRatio);
29979-
29980-
SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
29981-
Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
29982-
return DAG.getBitcast(N0.getValueType(), NewShuffle);
29983-
}
29984-
2998529896
/// If both input operands of a logic op are being cast from floating point
2998629897
/// types, try to convert this into a floating point logic node to avoid
2998729898
/// unnecessary moves from SSE to integer registers.
@@ -30059,9 +29970,6 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
3005929970
if (DCI.isBeforeLegalizeOps())
3006029971
return SDValue();
3006129972

30062-
if (SDValue Zext = combineVectorZext(N, DAG, DCI, Subtarget))
30063-
return Zext;
30064-
3006529973
if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
3006629974
return R;
3006729975

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