@@ -29893,95 +29893,6 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
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}
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}
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- static SDValue combineVectorZext(SDNode *N, SelectionDAG &DAG,
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- TargetLowering::DAGCombinerInfo &DCI,
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- const X86Subtarget &Subtarget) {
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- SDValue N0 = N->getOperand(0);
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- SDValue N1 = N->getOperand(1);
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- SDLoc DL(N);
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-
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- // A vector zext_in_reg may be represented as a shuffle,
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- // feeding into a bitcast (this represents anyext) feeding into
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- // an and with a mask.
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- // We'd like to try to combine that into a shuffle with zero
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- // plus a bitcast, removing the and.
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- if (N0.getOpcode() != ISD::BITCAST ||
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- N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
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- return SDValue();
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-
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- // The other side of the AND should be a splat of 2^C, where C
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- // is the number of bits in the source type.
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- N1 = peekThroughBitcasts(N1);
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- if (N1.getOpcode() != ISD::BUILD_VECTOR)
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- return SDValue();
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- BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
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-
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- ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
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- EVT SrcType = Shuffle->getValueType(0);
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-
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- // We expect a single-source shuffle
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- if (!Shuffle->getOperand(1)->isUndef())
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- return SDValue();
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-
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- unsigned SrcSize = SrcType.getScalarSizeInBits();
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- unsigned NumElems = SrcType.getVectorNumElements();
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-
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- APInt SplatValue, SplatUndef;
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- unsigned SplatBitSize;
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- bool HasAnyUndefs;
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- if (!Vector->isConstantSplat(SplatValue, SplatUndef,
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- SplatBitSize, HasAnyUndefs))
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- return SDValue();
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-
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- unsigned ResSize = N1.getScalarValueSizeInBits();
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- // Make sure the splat matches the mask we expect
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- if (SplatBitSize > ResSize ||
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- (SplatValue + 1).exactLogBase2() != (int)SrcSize)
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- return SDValue();
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-
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- // Make sure the input and output size make sense
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- if (SrcSize >= ResSize || ResSize % SrcSize)
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- return SDValue();
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-
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- // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
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- // The number of u's between each two values depends on the ratio between
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- // the source and dest type.
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- unsigned ZextRatio = ResSize / SrcSize;
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- bool IsZext = true;
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- for (unsigned i = 0; i != NumElems; ++i) {
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- if (i % ZextRatio) {
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- if (Shuffle->getMaskElt(i) > 0) {
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- // Expected undef
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- IsZext = false;
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- break;
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- }
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- } else {
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- if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
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- // Expected element number
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- IsZext = false;
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- break;
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- }
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- }
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- }
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-
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- if (!IsZext)
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- return SDValue();
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-
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- // Ok, perform the transformation - replace the shuffle with
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- // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
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- // (instead of undef) where the k elements come from the zero vector.
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- SmallVector<int, 8> Mask;
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- for (unsigned i = 0; i != NumElems; ++i)
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- if (i % ZextRatio)
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- Mask.push_back(NumElems);
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- else
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- Mask.push_back(i / ZextRatio);
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-
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- SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
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- Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
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- return DAG.getBitcast(N0.getValueType(), NewShuffle);
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- }
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-
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/// If both input operands of a logic op are being cast from floating point
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/// types, try to convert this into a floating point logic node to avoid
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/// unnecessary moves from SSE to integer registers.
@@ -30059,9 +29970,6 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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- if (SDValue Zext = combineVectorZext(N, DAG, DCI, Subtarget))
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- return Zext;
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-
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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