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samkoltonsamkolton
committedNov 15, 2016
[AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>
Summary: This is needed to be able to use this flags in InstrMappings. Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D26666 llvm-svn: 286960
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‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,7 @@ multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> {
155155
class MIMG_Sampler_Helper <bits<7> op, string asm,
156156
RegisterClass dst_rc,
157157
RegisterClass src_rc,
158-
int wqm,
158+
bit wqm,
159159
string dns=""> : MIMG_Helper <
160160
(outs dst_rc:$vdata),
161161
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
@@ -168,7 +168,7 @@ class MIMG_Sampler_Helper <bits<7> op, string asm,
168168

169169
multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
170170
RegisterClass dst_rc,
171-
int channels, int wqm> {
171+
int channels, bit wqm> {
172172
def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,
173173
!if(!eq(channels, 1), "AMDGPU", "")>,
174174
MIMG_Mask<asm#"_V1", channels>;
@@ -182,7 +182,7 @@ multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
182182
MIMG_Mask<asm#"_V16", channels>;
183183
}
184184

185-
multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {
185+
multiclass MIMG_Sampler <bits<7> op, string asm, bit wqm=0> {
186186
defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
187187
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
188188
defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
@@ -193,7 +193,7 @@ multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>;
193193

194194
class MIMG_Gather_Helper <bits<7> op, string asm,
195195
RegisterClass dst_rc,
196-
RegisterClass src_rc, int wqm> : MIMG <
196+
RegisterClass src_rc, bit wqm> : MIMG <
197197
(outs dst_rc:$vdata),
198198
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
199199
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
@@ -219,7 +219,7 @@ class MIMG_Gather_Helper <bits<7> op, string asm,
219219

220220
multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
221221
RegisterClass dst_rc,
222-
int channels, int wqm> {
222+
int channels, bit wqm> {
223223
def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
224224
MIMG_Mask<asm#"_V1", channels>;
225225
def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
@@ -232,7 +232,7 @@ multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
232232
MIMG_Mask<asm#"_V16", channels>;
233233
}
234234

235-
multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> {
235+
multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
236236
defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
237237
defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
238238
defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;

‎llvm/lib/Target/AMDGPU/SIInstrFormats.td

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -15,59 +15,59 @@ class InstSI <dag outs, dag ins, string asm = "",
1515
list<dag> pattern = []> :
1616
AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
1717

18-
field bits<1> VM_CNT = 0;
19-
field bits<1> EXP_CNT = 0;
20-
field bits<1> LGKM_CNT = 0;
21-
22-
field bits<1> SALU = 0;
23-
field bits<1> VALU = 0;
24-
25-
field bits<1> SOP1 = 0;
26-
field bits<1> SOP2 = 0;
27-
field bits<1> SOPC = 0;
28-
field bits<1> SOPK = 0;
29-
field bits<1> SOPP = 0;
30-
31-
field bits<1> VOP1 = 0;
32-
field bits<1> VOP2 = 0;
33-
field bits<1> VOP3 = 0;
34-
field bits<1> VOPC = 0;
35-
field bits<1> SDWA = 0;
36-
field bits<1> DPP = 0;
37-
38-
field bits<1> MUBUF = 0;
39-
field bits<1> MTBUF = 0;
40-
field bits<1> SMRD = 0;
41-
field bits<1> DS = 0;
42-
field bits<1> MIMG = 0;
43-
field bits<1> FLAT = 0;
18+
field bit VM_CNT = 0;
19+
field bit EXP_CNT = 0;
20+
field bit LGKM_CNT = 0;
21+
22+
field bit SALU = 0;
23+
field bit VALU = 0;
24+
25+
field bit SOP1 = 0;
26+
field bit SOP2 = 0;
27+
field bit SOPC = 0;
28+
field bit SOPK = 0;
29+
field bit SOPP = 0;
30+
31+
field bit VOP1 = 0;
32+
field bit VOP2 = 0;
33+
field bit VOP3 = 0;
34+
field bit VOPC = 0;
35+
field bit SDWA = 0;
36+
field bit DPP = 0;
37+
38+
field bit MUBUF = 0;
39+
field bit MTBUF = 0;
40+
field bit SMRD = 0;
41+
field bit DS = 0;
42+
field bit MIMG = 0;
43+
field bit FLAT = 0;
4444

4545
// Whether WQM _must_ be enabled for this instruction.
46-
field bits<1> WQM = 0;
47-
field bits<1> VGPRSpill = 0;
48-
field bits<1> SGPRSpill = 0;
46+
field bit WQM = 0;
47+
field bit VGPRSpill = 0;
48+
field bit SGPRSpill = 0;
4949

5050
// This bit tells the assembler to use the 32-bit encoding in case it
5151
// is unable to infer the encoding from the operands.
52-
field bits<1> VOPAsmPrefer32Bit = 0;
52+
field bit VOPAsmPrefer32Bit = 0;
5353

54-
field bits<1> Gather4 = 0;
54+
field bit Gather4 = 0;
5555

5656
// Whether WQM _must_ be disabled for this instruction.
57-
field bits<1> DisableWQM = 0;
57+
field bit DisableWQM = 0;
5858

5959
// Most sopk treat the immediate as a signed 16-bit, however some
6060
// use it as unsigned.
61-
field bits<1> SOPKZext = 0;
61+
field bit SOPKZext = 0;
6262

6363
// This is an s_store_dword* instruction that requires a cache flush
6464
// on wave termination. It is necessary to distinguish from mayStore
6565
// SMEM instructions like the cache flush ones.
66-
field bits<1> ScalarStore = 0;
66+
field bit ScalarStore = 0;
6767

6868
// Whether the operands can be ignored when computing the
6969
// instruction size.
70-
field bits<1> FixedSize = 0;
70+
field bit FixedSize = 0;
7171

7272
// These need to be kept in sync with the enum in SIInstrFlags.
7373
let TSFlags{0} = VM_CNT;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1045,18 +1045,18 @@ multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
10451045
def getVOPe64 : InstrMapping {
10461046
let FilterClass = "VOP";
10471047
let RowFields = ["OpName"];
1048-
let ColFields = ["Size"];
1049-
let KeyCol = ["4"];
1050-
let ValueCols = [["8"]];
1048+
let ColFields = ["Size", "VOP3"];
1049+
let KeyCol = ["4", "0"];
1050+
let ValueCols = [["8", "1"]];
10511051
}
10521052

10531053
// Maps an opcode in e64 form to its e32 equivalent
10541054
def getVOPe32 : InstrMapping {
10551055
let FilterClass = "VOP";
10561056
let RowFields = ["OpName"];
1057-
let ColFields = ["Size"];
1058-
let KeyCol = ["8"];
1059-
let ValueCols = [["4"]];
1057+
let ColFields = ["Size", "VOP3"];
1058+
let KeyCol = ["8", "1"];
1059+
let ValueCols = [["4", "0"]];
10601060
}
10611061

10621062
def getMaskedMIMGOp : InstrMapping {

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