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author
Dylan McKay
committedNov 9, 2016
[AVR] Add a selection of CodeGen tests
Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
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‎llvm/test/CodeGen/AVR/atomics/load32.ll

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; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; CHECK-LABEL: atomic_load32
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; CHECK: call __sync_val_compare_and_swap_4
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define i32 @atomic_load32(i32* %foo) {
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%val = load atomic i32, i32* %foo unordered, align 4
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ret i32 %val
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}
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; CHECK-LABEL: atomic_load_sub32
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; CHECK: call __sync_fetch_and_sub_4
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define i32 @atomic_load_sub32(i32* %foo) {
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%val = atomicrmw sub i32* %foo, i32 13 seq_cst
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ret i32 %val
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}
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‎llvm/test/CodeGen/AVR/atomics/load64.ll

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; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; CHECK-LABEL: atomic_load64
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; CHECK: call __sync_val_compare_and_swap_8
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define i64 @atomic_load64(i64* %foo) {
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%val = load atomic i64, i64* %foo unordered, align 8
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ret i64 %val
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}
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; CHECK-LABEL: atomic_load_sub64
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; CHECK: call __sync_fetch_and_sub_8
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define i64 @atomic_load_sub64(i64* %foo) {
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%val = atomicrmw sub i64* %foo, i64 13 seq_cst
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ret i64 %val
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}
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‎llvm/test/CodeGen/AVR/atomics/swap.ll

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; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
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; CHECK-LABEL: atomic_swap8
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; CHECK: call __sync_lock_test_and_set_1
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define i8 @atomic_swap8(i8* %foo) {
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%val = atomicrmw xchg i8* %foo, i8 13 seq_cst
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ret i8 %val
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}
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; CHECK-LABEL: atomic_swap16
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; CHECK: call __sync_lock_test_and_set_2
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define i16 @atomic_swap16(i16* %foo) {
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%val = atomicrmw xchg i16* %foo, i16 13 seq_cst
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ret i16 %val
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}
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; CHECK-LABEL: atomic_swap32
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; CHECK: call __sync_lock_test_and_set_4
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define i32 @atomic_swap32(i32* %foo) {
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%val = atomicrmw xchg i32* %foo, i32 13 seq_cst
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ret i32 %val
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}
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; CHECK-LABEL: atomic_swap64
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; CHECK: call __sync_lock_test_and_set_8
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define i64 @atomic_swap64(i64* %foo) {
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%val = atomicrmw xchg i64* %foo, i64 13 seq_cst
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ret i64 %val
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}
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‎llvm/test/CodeGen/AVR/ctpop.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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define i8 @count_population(i8) unnamed_addr {
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entry-block:
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%1 = tail call i8 @llvm.ctpop.i8(i8 %0)
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ret i8 %1
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}
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declare i8 @llvm.ctpop.i8(i8)
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; CHECK-LABEL: count_population:
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; CHECK: mov [[SCRATCH:r[0-9]+]], [[RESULT:r[0-9]+]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: andi {{.*}}[[SCRATCH]], 85
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; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
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; CHECK: andi {{.*}}[[SCRATCH]], 51
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; CHECK: lsr {{.*}}[[RESULT]]
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; CHECK: lsr {{.*}}[[RESULT]]
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; CHECK: andi {{.*}}[[RESULT]], 51
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; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: lsr {{.*}}[[SCRATCH]]
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; CHECK: add {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
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; CHECK: andi {{.*}}[[SCRATCH]], 15
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; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
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; CHECK: ret

‎llvm/test/CodeGen/AVR/div.ll

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; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
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; Unsigned 8-bit division
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define i8 @udiv8(i8 %a, i8 %b) {
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; CHECK-LABEL: div8:
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; CHECK: call __udivmodqi4
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; CHECK-NEXT: ret
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%quotient = udiv i8 %a, %b
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ret i8 %quotient
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}
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; Signed 8-bit division
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define i8 @sdiv8(i8 %a, i8 %b) {
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; CHECK-LABEL: sdiv8:
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; CHECK: call __divmodqi4
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; CHECK-NEXT: ret
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%quotient = sdiv i8 %a, %b
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ret i8 %quotient
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}
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; Unsigned 16-bit division
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define i16 @udiv16(i16 %a, i16 %b) {
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; CHECK-LABEL: udiv16:
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; CHECK: call __udivmodhi4
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; CHECK-NEXT: movw r24, r22
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; CHECK-NEXT: ret
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%quot = udiv i16 %a, %b
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ret i16 %quot
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}
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; Signed 16-bit division
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define i16 @sdiv16(i16 %a, i16 %b) {
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; CHECK-LABEL: sdiv16:
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; CHECK: call __divmodhi4
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; CHECK-NEXT: movw r24, r22
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; CHECK-NEXT: ret
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%quot = sdiv i16 %a, %b
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ret i16 %quot
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}
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; Unsigned 32-bit division
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define i32 @udiv32(i32 %a, i32 %b) {
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; CHECK-LABEL: udiv32:
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; CHECK: call __udivmodsi4
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; CHECK-NEXT: movw r22, r18
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; CHECK-NEXT: movw r24, r20
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; CHECK-NEXT: ret
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%quot = udiv i32 %a, %b
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ret i32 %quot
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}
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; Signed 32-bit division
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define i32 @sdiv32(i32 %a, i32 %b) {
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; CHECK-LABEL: sdiv32:
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; CHECK: call __divmodsi4
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; CHECK-NEXT: movw r22, r18
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; CHECK-NEXT: movw r24, r20
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; CHECK-NEXT: ret
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%quot = sdiv i32 %a, %b
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ret i32 %quot
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}
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‎llvm/test/CodeGen/AVR/features/avr-tiny.ll

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; RUN: llc -mattr=avrtiny -O0 < %s -march=avr | FileCheck %s
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define i16 @reg_copy16(i16 %a) {
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; CHECK-LABEL: reg_copy16
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; CHECK: mov r18, r24
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; CHECK: mov r19, r25
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ret i16 %a
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}

‎llvm/test/CodeGen/AVR/features/avr25.ll

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; RUN: llc -mattr=avr25 -O0 < %s -march=avr | FileCheck %s
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; On most cores, the 16-bit 'MOVW' instruction can be used
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define i16 @reg_copy16(i16 %a) {
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; CHECK-LABEL: reg_copy16
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; CHECK: movw r18, r24
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ret i16 %a
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}

‎llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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; Test case for an assertion error.
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;
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; Error:
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; ```
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; Impossible reg-to-reg copy
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; UNREACHABLE executed at lib/Target/AVR/AVRInstrInfo.cpp
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; ```
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;
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; This no longer occurs.
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declare { i16, i1 } @llvm.umul.with.overflow.i16(i16, i16)
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; CHECK-LABEL: foo
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define void @foo() {
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entry-block:
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%0 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef)
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%1 = extractvalue { i16, i1 } %0, 1
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%2 = icmp eq i1 %1, true
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br i1 %2, label %cond, label %next
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next: ; preds = %entry-block
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ret void
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cond: ; preds = %entry-block
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unreachable
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}

‎llvm/test/CodeGen/AVR/inline-asm2.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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; CHECK-LABEL: foo
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define void @foo(i16 %a) {
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call void asm sideeffect "add $0, $0", "Z"(i16 %a) nounwind
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ret void
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}
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‎llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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declare i16 @llvm.bswap.i16(i16)
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define i16 @foo(i16) {
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; CHECK-LABEL: foo:
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entry-block:
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%1 = tail call i16 @llvm.bswap.i16(i16 %0)
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ret i16 %1
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}

‎llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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define void @foo(i1) {
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; CHECK-LABEL: foo:
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; CHECK: ret
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ret void
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}

‎llvm/test/CodeGen/AVR/mul.ll

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; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
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define i8 @mult8(i8 %a, i8 %b) {
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; CHECK-LABEL: mult8:
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; CHECK: muls r22, r24
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; CHECK: eor r1, r1
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; CHECK: mov r24, r0
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%mul = mul i8 %b, %a
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ret i8 %mul
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}
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define i16 @mult16(i16 %a, i16 %b) {
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; CHECK-LABEL: mult16:
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; CHECK: muls r22, r25
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; CHECK: mov r18, r0
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; CHECK: mul r22, r24
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; CHECK: mov r19, r0
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; CHECK: mov r20, r1
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; CHECK: eor r1, r1
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; CHECK: add r20, r18
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; CHECK: muls r23, r24
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; CHECK: eor r1, r1
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; CHECK: mov r22, r0
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; CHECK: add r22, r20
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; :TODO: finish after reworking shift instructions
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%mul = mul nsw i16 %b, %a
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ret i16 %mul
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}

‎llvm/test/CodeGen/AVR/neg.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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define i8 @neg8(i8 %x) {
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; CHECK-LABEL: neg8:
5+
; CHECK: neg r24
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%sub = sub i8 0, %x
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ret i8 %sub
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}

‎llvm/test/CodeGen/AVR/progmem-extended.ll

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; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s
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; Tests the extended LPM instructions (LPMW, LPM Rd, Z+).
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define i8 @test8(i8 addrspace(1)* %p) {
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; CHECK-LABEL: test8:
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; CHECK: movw r30, r24
8+
; CHECK: lpm r24, Z
9+
%1 = load i8, i8 addrspace(1)* %p
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ret i8 %1
11+
}
12+
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define i16 @test16(i16 addrspace(1)* %p) {
14+
; CHECK-LABEL: test16:
15+
; CHECK: movw r30, r24
16+
; CHECK: lpmw r24, Z
17+
%1 = load i16, i16 addrspace(1)* %p
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ret i16 %1
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}
20+
21+
define i8 @test8postinc(i8 addrspace(1)* %x, i8 %y) {
22+
; CHECK-LABEL: test8postinc:
23+
; CHECK: movw r30, r24
24+
; CHECK: lpm {{.*}}, Z+
25+
entry:
26+
%cmp10 = icmp sgt i8 %y, 0
27+
br i1 %cmp10, label %for.body, label %for.end
28+
29+
for.body: ; preds = %entry, %for.body
30+
%ret.013 = phi i8 [ %add, %for.body ], [ 0, %entry ]
31+
%i.012 = phi i8 [ %inc, %for.body ], [ 0, %entry ]
32+
%x.addr.011 = phi i8 addrspace(1)* [ %incdec.ptr, %for.body ], [ %x, %entry ]
33+
%incdec.ptr = getelementptr inbounds i8, i8 addrspace(1)* %x.addr.011, i16 1
34+
%0 = load i8, i8 addrspace(1)* %x.addr.011
35+
%add = add i8 %0, %ret.013
36+
%inc = add i8 %i.012, 1
37+
%exitcond = icmp eq i8 %inc, %y
38+
br i1 %exitcond, label %for.end, label %for.body
39+
40+
for.end: ; preds = %for.body, %entry
41+
%ret.0.lcssa = phi i8 [ 0, %entry ], [ %add, %for.body ]
42+
ret i8 %ret.0.lcssa
43+
}
44+
45+
define i16 @test16postinc(i16 addrspace(1)* %x, i8 %y) {
46+
; CHECK-LABEL: test16postinc:
47+
; CHECK: movw r30, r24
48+
; CHECK: lpmw {{.*}}, Z+
49+
entry:
50+
%cmp5 = icmp sgt i8 %y, 0
51+
br i1 %cmp5, label %for.body, label %for.end
52+
53+
for.body: ; preds = %entry, %for.body
54+
%ret.08 = phi i16 [ %add, %for.body ], [ 0, %entry ]
55+
%i.07 = phi i8 [ %inc, %for.body ], [ 0, %entry ]
56+
%x.addr.06 = phi i16 addrspace(1)* [ %incdec.ptr, %for.body ], [ %x, %entry ]
57+
%incdec.ptr = getelementptr inbounds i16, i16 addrspace(1)* %x.addr.06, i16 1
58+
%0 = load i16, i16 addrspace(1)* %x.addr.06
59+
%add = add nsw i16 %0, %ret.08
60+
%inc = add i8 %i.07, 1
61+
%exitcond = icmp eq i8 %inc, %y
62+
br i1 %exitcond, label %for.end, label %for.body
63+
64+
for.end: ; preds = %for.body, %entry
65+
%ret.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
66+
ret i16 %ret.0.lcssa
67+
}

‎llvm/test/CodeGen/AVR/rem.ll

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; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
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; Unsigned 8-bit remision
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define i8 @urem8(i8 %a, i8 %b) {
5+
; CHECK-LABEL: rem8:
6+
; CHECK: call __udivmodqi4
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; CHECK-NEXT: mov r24, r25
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; CHECK-NEXT: ret
9+
%rem = urem i8 %a, %b
10+
ret i8 %rem
11+
}
12+
13+
; Signed 8-bit remision
14+
define i8 @srem8(i8 %a, i8 %b) {
15+
; CHECK-LABEL: srem8:
16+
; CHECK: call __divmodqi4
17+
; CHECK-NEXT: mov r24, r25
18+
; CHECK-NEXT: ret
19+
%rem = srem i8 %a, %b
20+
ret i8 %rem
21+
}
22+
23+
; Unsigned 16-bit remision
24+
define i16 @urem16(i16 %a, i16 %b) {
25+
; CHECK-LABEL: urem16:
26+
; CHECK: call __udivmodhi4
27+
; CHECK-NEXT: ret
28+
%rem = urem i16 %a, %b
29+
ret i16 %rem
30+
}
31+
32+
; Signed 16-bit remision
33+
define i16 @srem16(i16 %a, i16 %b) {
34+
; CHECK-LABEL: srem16:
35+
; CHECK: call __divmodhi4
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; CHECK-NEXT: ret
37+
%rem = srem i16 %a, %b
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ret i16 %rem
39+
}
40+
41+
; Unsigned 32-bit remision
42+
define i32 @urem32(i32 %a, i32 %b) {
43+
; CHECK-LABEL: urem32:
44+
; CHECK: call __udivmodsi4
45+
; CHECK-NEXT: ret
46+
%rem = urem i32 %a, %b
47+
ret i32 %rem
48+
}
49+
50+
; Signed 32-bit remision
51+
define i32 @srem32(i32 %a, i32 %b) {
52+
; CHECK-LABEL: srem32:
53+
; CHECK: call __divmodsi4
54+
; CHECK-NEXT: ret
55+
%rem = srem i32 %a, %b
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ret i32 %rem
57+
}
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‎llvm/test/CodeGen/AVR/runtime-trig.ll

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; RUN: llc < %s -march=avr | FileCheck %s
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; Checks that `sin` and `cos` nodes are expanded into calls to
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; the `sin` and `cos` runtime library functions.
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; On AVR, the only floats supported are 32-bits, and so the
6+
; function names have no `f` or `d` suffix.
7+
8+
declare float @llvm.sin.f32(float %x)
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declare float @llvm.cos.f32(float %x)
10+
11+
define float @do_sin(float %a) {
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; CHECK-LABEL: do_sin:
13+
; CHECK: {{sin$}}
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%result = call float @llvm.sin.f32(float %a)
15+
ret float %result
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}
17+
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; CHECK-LABEL: do_cos:
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; CHECK: {{cos$}}
20+
define float @do_cos(float %a) {
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%result = call float @llvm.cos.f32(float %a)
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ret float %result
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}

‎llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll

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; RUN: llc -march=avr -print-after=expand-isel-pseudos < %s 2>&1 | FileCheck %s
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; Because `switch` seems to trigger Machine Basic Blocks to be ordered
4+
; in a different order than they were constructed, this exposes an
5+
; error in the `expand-isel-pseudos` pass. Specifically, it thought we
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; could always fallthrough to a newly-constructed MBB. However,
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; there's no guarantee that either of the constructed MBBs need to
8+
; occur immediately after the currently-focused one!
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;
10+
; This issue manifests in a CFG that looks something like this:
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;
12+
; BB#2: derived from LLVM BB %finish
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; Predecessors according to CFG: BB#0 BB#1
14+
; %vreg0<def> = PHI %vreg3, <BB#0>, %vreg5, <BB#1>
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; %vreg7<def> = LDIRdK 2
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; %vreg8<def> = LDIRdK 1
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; CPRdRr %vreg2, %vreg0, %SREG<imp-def>
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; BREQk <BB#6>, %SREG<imp-use>
19+
; Successors according to CFG: BB#5(?%) BB#6(?%)
20+
;
21+
; The code assumes it the fallthrough block after this is BB#5, but
22+
; it's actually BB#3! To be proper, there should be an unconditional
23+
; jump tying this block to BB#5.
24+
25+
define i8 @select_must_add_unconditional_jump(i8 %arg0, i8 %arg1) unnamed_addr {
26+
entry-block:
27+
switch i8 %arg0, label %dead [
28+
i8 0, label %zero
29+
i8 1, label %one
30+
]
31+
32+
zero:
33+
br label %finish
34+
35+
one:
36+
br label %finish
37+
38+
finish:
39+
%predicate = phi i8 [ 50, %zero ], [ 100, %one ]
40+
%is_eq = icmp eq i8 %arg1, %predicate
41+
%result = select i1 %is_eq, i8 1, i8 2
42+
ret i8 %result
43+
44+
dead:
45+
ret i8 0
46+
}
47+
48+
; This check may be a bit brittle, but the important thing is that the
49+
; basic block containing `select` needs to contain explicit jumps to
50+
; both successors.
51+
52+
; CHECK: BB#2: derived from LLVM BB %finish
53+
; CHECK: BREQk <[[BRANCHED:BB#[0-9]+]]>
54+
; CHECK: RJMPk <[[DIRECT:BB#[0-9]+]]>
55+
; CHECK: Successors according to CFG
56+
; CHECK-SAME-DAG: {{.*}}[[BRANCHED]]
57+
; CHECK-SAME-DAG: {{.*}}[[DIRECT]]
58+
; CHECK: BB#3: derived from LLVM BB

‎llvm/test/CodeGen/AVR/sign-extension.ll

+71
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
; RUN: llc -march=avr < %s | FileCheck %s
2+
3+
define i8 @sign_extended_1_to_8(i1) {
4+
; CHECK-LABEL: sign_extended_1_to_8
5+
entry-block:
6+
%1 = sext i1 %0 to i8
7+
ret i8 %1
8+
}
9+
10+
define i16 @sign_extended_1_to_16(i1) {
11+
; CHECK-LABEL: sign_extended_1_to_16
12+
entry-block:
13+
%1 = sext i1 %0 to i16
14+
ret i16 %1
15+
}
16+
17+
define i16 @sign_extended_8_to_16(i8) {
18+
; CHECK-LABEL: sign_extended_8_to_16
19+
entry-block:
20+
%1 = sext i8 %0 to i16
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ret i16 %1
22+
}
23+
24+
define i32 @sign_extended_1_to_32(i1) {
25+
; CHECK-LABEL: sign_extended_1_to_32
26+
entry-block:
27+
%1 = sext i1 %0 to i32
28+
ret i32 %1
29+
}
30+
31+
define i32 @sign_extended_8_to_32(i8) {
32+
; CHECK-LABEL: sign_extended_8_to_32
33+
entry-block:
34+
%1 = sext i8 %0 to i32
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ret i32 %1
36+
}
37+
38+
define i32 @sign_extended_16_to_32(i16) {
39+
; CHECK-LABEL: sign_extended_16_to_32
40+
entry-block:
41+
%1 = sext i16 %0 to i32
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ret i32 %1
43+
}
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45+
define i64 @sign_extended_1_to_64(i1) {
46+
; CHECK-LABEL: sign_extended_1_to_64
47+
entry-block:
48+
%1 = sext i1 %0 to i64
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ret i64 %1
50+
}
51+
52+
define i64 @sign_extended_8_to_64(i8) {
53+
; CHECK-LABEL: sign_extended_8_to_64
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entry-block:
55+
%1 = sext i8 %0 to i64
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ret i64 %1
57+
}
58+
59+
define i64 @sign_extended_16_to_64(i16) {
60+
; CHECK-LABEL: sign_extended_16_to_64
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entry-block:
62+
%1 = sext i16 %0 to i64
63+
ret i64 %1
64+
}
65+
66+
define i64 @sign_extended_32_to_64(i32) {
67+
; CHECK-LABEL: sign_extended_32_to_64
68+
entry-block:
69+
%1 = sext i32 %0 to i64
70+
ret i64 %1
71+
}

‎llvm/test/CodeGen/AVR/trunc.ll

+18
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
; RUN: llc < %s -march=avr | FileCheck %s
2+
3+
define i8 @trunc8_loreg(i16 %x, i16 %y) {
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; CHECK-LABEL: trunc8_loreg:
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; CHECK: mov r24, r22
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; CHECK-NEXT: ret
7+
%conv = trunc i16 %y to i8
8+
ret i8 %conv
9+
}
10+
11+
define i8 @trunc8_hireg(i16 %x, i16 %y) {
12+
; CHECK-LABEL: trunc8_hireg:
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; CHECK: mov r24, r23
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; CHECK-NEXT: ret
15+
%shr1 = lshr i16 %y, 8
16+
%conv = trunc i16 %shr1 to i8
17+
ret i8 %conv
18+
}

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