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author
Ron Lieberman
committedAug 1, 2016
[Hexagon] Generate vector printing instructions
llvm-svn: 277370
·
llvmorg-21-initllvmorg-4.0.0-rc1
1 parent 38115ff commit 8123b96

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‎llvm/lib/Target/Hexagon/CMakeLists.txt

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@@ -54,6 +54,7 @@ add_llvm_target(HexagonCodeGen
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HexagonTargetMachine.cpp
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HexagonTargetObjectFile.cpp
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HexagonTargetTransformInfo.cpp
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HexagonVectorPrint.cpp
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HexagonVLIWPacketizer.cpp
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RDFCopy.cpp
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RDFDeadCode.cpp

‎llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

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@@ -86,6 +86,10 @@ static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
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static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
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cl::Hidden, cl::desc("Disable backend optimizations"));
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static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Enable Hexagon Vector print instr pass"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
@@ -135,6 +139,7 @@ namespace llvm {
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonSplitDoubleRegs();
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FunctionPass *createHexagonStoreWidening();
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FunctionPass *createHexagonVectorPrint();
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} // end namespace llvm;
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
@@ -331,6 +336,8 @@ void HexagonPassConfig::addPreEmitPass() {
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addPass(createHexagonPacketizer(), false);
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}
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if (EnableVectorPrint)
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addPass(createHexagonVectorPrint(), false);
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// Add CFI instructions if necessary.
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addPass(createHexagonCallFrameInformation(), false);

‎llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp

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//===-- HexagonVectorPrint.cpp - Generate vector printing instructions -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass adds the capability to generate pseudo vector/predicate register
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// printing instructions. These pseudo instructions should be used with the
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// simulator, NEVER on hardware.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hexagon-vector-print"
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#include "HexagonTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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namespace llvm {
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FunctionPass *createHexagonVectorPrint();
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void initializeHexagonVectorPrintPass(PassRegistry&);
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}
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namespace {
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class HexagonVectorPrint : public MachineFunctionPass {
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const HexagonSubtarget *QST;
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const HexagonInstrInfo *QII;
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const HexagonRegisterInfo *QRI;
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public:
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static char ID;
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HexagonVectorPrint() : MachineFunctionPass(ID),
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QST(0), QII(0), QRI(0) {
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initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
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}
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const char *getPassName() const override {
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return "Hexagon VectorPrint pass";
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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};
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char HexagonVectorPrint::ID = 0;
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static bool isVecReg(unsigned Reg) {
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return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
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|| (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
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|| (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
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}
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std::string getStringReg(unsigned R) {
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if (R >= Hexagon::V0 && R <= Hexagon::V31) {
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static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
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"28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
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"30", "31", "32", "33", "34", "35", "36", "37",
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"38", "39", "3a", "3b", "3c", "3d", "3e", "3f"};
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return S[R-Hexagon::V0];
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}
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if (R >= Hexagon::Q0 && R <= Hexagon::Q3) {
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static const char* S[] = { "00", "01", "02", "03"};
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return S[R-Hexagon::Q0];
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}
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llvm_unreachable("valid vreg");
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}
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static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
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MachineBasicBlock::instr_iterator I,
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const DebugLoc &DL, const HexagonInstrInfo *QII,
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MachineFunction &Fn) {
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std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
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const char *cstr = Fn.createExternalSymbolName(VDescStr.c_str());
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unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
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BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
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.addExternalSymbol(cstr)
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.addImm(ExtraInfo);
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}
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static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
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if (MI.getNumOperands() < 1) return false;
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// Vec load or compute.
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if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
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Reg = MI.getOperand(0).getReg();
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if (isVecReg(Reg))
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return true;
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}
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// Vec store.
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if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
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Reg = MI.getOperand(2).getReg();
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if (isVecReg(Reg))
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return true;
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}
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// Vec store post increment.
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if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
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Reg = MI.getOperand(3).getReg();
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if (isVecReg(Reg))
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return true;
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}
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return false;
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}
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bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
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bool Changed = false;
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QST = &Fn.getSubtarget<HexagonSubtarget>();
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QRI = QST->getRegisterInfo();
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QII = QST->getInstrInfo();
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std::vector<MachineInstr *> VecPrintList;
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for (auto &MBB : Fn)
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for (auto &MI : MBB) {
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if (MI.isBundle()) {
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MachineBasicBlock::instr_iterator MII = MI.getIterator();
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for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
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if (MII->getNumOperands() < 1) continue;
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unsigned Reg = 0;
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if (getInstrVecReg(*MII, Reg)) {
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VecPrintList.push_back((&*MII));
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DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump());
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}
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}
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} else {
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unsigned Reg = 0;
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if (getInstrVecReg(MI, Reg)) {
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VecPrintList.push_back(&MI);
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DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
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}
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}
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}
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Changed = VecPrintList.size() > 0;
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if (!Changed) return Changed;
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for (auto *I : VecPrintList) {
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DebugLoc DL = I->getDebugLoc();
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MachineBasicBlock *MBB = I->getParent();
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DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
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unsigned Reg = 0;
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assert(getInstrVecReg(*I, Reg) && "Need a vector reg");
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MachineBasicBlock::instr_iterator MII = I->getIterator();
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if (I->isInsideBundle()) {
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DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
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while (MII->isInsideBundle()) ++MII;
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} else {
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DEBUG(dbgs() << "add after instruction\n"; I->dump());
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MII++;
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}
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if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
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DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n');
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addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
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} else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
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DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n');
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addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
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MII, DL, QII, Fn);
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addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
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MII, DL, QII, Fn);
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} else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
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DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n');
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addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
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} else
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llvm_unreachable("Bad Vector reg");
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}
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return Changed;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
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"Hexagon VectorPrint pass", false, false)
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FunctionPass *llvm::createHexagonVectorPrint() {
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return new HexagonVectorPrint();
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}

‎llvm/test/CodeGen/Hexagon/v6vec-vprint.ll

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; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
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; generate .long XXXX which is a vector debug print instruction.
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; CHECK: .long 0x1dffe0
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @do_vecs(i8* nocapture readonly %a, i8* nocapture readonly %b, i8* nocapture %c) #0 {
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entry:
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%0 = bitcast i8* %a to <16 x i32>*
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%1 = load <16 x i32>, <16 x i32>* %0, align 4, !tbaa !1
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%2 = bitcast i8* %b to <16 x i32>*
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%3 = load <16 x i32>, <16 x i32>* %2, align 4, !tbaa !1
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%4 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %1, <16 x i32> %3)
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%5 = bitcast i8* %c to <16 x i32>*
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store <16 x i32> %4, <16 x i32>* %5, align 4, !tbaa !1
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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!llvm.ident = !{!0}
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!0 = !{!"QuIC LLVM Hexagon Clang version 7.x-pre-unknown"}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}

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