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mkuperstmkuperst
committedJul 6, 2016
[X86] Transform setcc + movzbl into xorl + setcc
xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. Differential Revision: http://reviews.llvm.org/D21774 llvm-svn: 274692
1 parent 0a53fdf commit 1ef6c59

32 files changed

+523
-288
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‎llvm/lib/Target/X86/CMakeLists.txt

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@@ -19,6 +19,7 @@ set(sources
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X86FastISel.cpp
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X86FixupBWInsts.cpp
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X86FixupLEAs.cpp
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X86FixupSetCC.cpp
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X86FloatingPoint.cpp
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X86FrameLowering.cpp
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X86ISelDAGToDAG.cpp

‎llvm/lib/Target/X86/X86.h

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@@ -59,6 +59,9 @@ FunctionPass *createX86FixupLEAs();
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/// recalculations.
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FunctionPass *createX86OptimizeLEAs();
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/// Return a pass that transforms setcc + movzx pairs into xor + setcc.
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FunctionPass *createX86FixupSetCC();
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/// Return a pass that expands WinAlloca pseudo-instructions.
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FunctionPass *createX86WinAllocaExpander();
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‎llvm/lib/Target/X86/X86FixupSetCC.cpp

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@@ -0,0 +1,183 @@
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//===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pass that fixes zero-extension of setcc patterns.
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// X86 setcc instructions are modeled to have no input arguments, and a single
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// GR8 output argument. This is consistent with other similar instructions
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// (e.g. movb), but means it is impossible to directly generate a setcc into
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// the lower GR8 of a specified GR32.
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// This means that ISel must select (zext (setcc)) into something like
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// seta %al; movzbl %al, %eax.
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// Unfortunately, this can cause a stall due to the partial register write
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// performed by the setcc. Instead, we can use:
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// xor %eax, %eax; seta %al
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// This both avoids the stall, and encodes shorter.
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-fixup-setcc"
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STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
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namespace {
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class X86FixupSetCCPass : public MachineFunctionPass {
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public:
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X86FixupSetCCPass() : MachineFunctionPass(ID) {}
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const char *getPassName() const override { return "X86 Fixup SetCC"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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// Find the preceding instruction that imp-defs eflags.
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MachineInstr *findFlagsImpDef(MachineBasicBlock *MBB,
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MachineBasicBlock::reverse_iterator MI);
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// Return true if MI imp-uses eflags.
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bool impUsesFlags(MachineInstr *MI);
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// Return true if this is the opcode of a SetCC instruction with a register
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// output.
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bool isSetCCr(unsigned Opode);
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MachineRegisterInfo *MRI;
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const X86InstrInfo *TII;
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enum { SearchBound = 16 };
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static char ID;
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};
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char X86FixupSetCCPass::ID = 0;
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}
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FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
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bool X86FixupSetCCPass::isSetCCr(unsigned Opcode) {
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switch (Opcode) {
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default:
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return false;
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case X86::SETOr:
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case X86::SETNOr:
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case X86::SETBr:
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case X86::SETAEr:
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case X86::SETEr:
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case X86::SETNEr:
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case X86::SETBEr:
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case X86::SETAr:
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case X86::SETSr:
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case X86::SETNSr:
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case X86::SETPr:
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case X86::SETNPr:
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case X86::SETLr:
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case X86::SETGEr:
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case X86::SETLEr:
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case X86::SETGr:
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return true;
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}
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}
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// We expect the instruction *immediately* before the setcc to imp-def
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// EFLAGS (because of scheduling glue). To make this less brittle w.r.t
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// scheduling, look backwards until we hit the beginning of the
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// basic-block, or a small bound (to avoid quadratic behavior).
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MachineInstr *
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X86FixupSetCCPass::findFlagsImpDef(MachineBasicBlock *MBB,
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MachineBasicBlock::reverse_iterator MI) {
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auto MBBStart = MBB->instr_rend();
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for (int i = 0; (i < SearchBound) && (MI != MBBStart); ++i, ++MI)
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for (auto &Op : MI->implicit_operands())
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if ((Op.getReg() == X86::EFLAGS) && (Op.isDef()))
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return &*MI;
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return nullptr;
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}
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bool X86FixupSetCCPass::impUsesFlags(MachineInstr *MI) {
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for (auto &Op : MI->implicit_operands())
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if ((Op.getReg() == X86::EFLAGS) && (Op.isUse()))
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return true;
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return false;
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}
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bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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MRI = &MF.getRegInfo();
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TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
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SmallVector<MachineInstr*, 4> ToErase;
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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// Find a setcc that is used by a zext.
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// This doesn't have to be the only use, the transformation is safe
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// regardless.
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if (!isSetCCr(MI.getOpcode()))
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continue;
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MachineInstr *ZExt = nullptr;
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for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
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if (Use.getOpcode() == X86::MOVZX32rr8)
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ZExt = &Use;
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if (!ZExt)
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continue;
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// Find the preceding instruction that imp-defs eflags.
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MachineInstr *FlagsDefMI = findFlagsImpDef(
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MI.getParent(), MachineBasicBlock::reverse_iterator(&MI));
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if (!FlagsDefMI)
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continue;
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// We'd like to put something that clobbers eflags directly before
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// FlagsDefMI. This can't hurt anything after FlagsDefMI, because
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// it, itself, by definition, clobbers eflags. But it may happen that
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// FlagsDefMI also *uses* eflags, in which case the transformation is
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// invalid.
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if (impUsesFlags(FlagsDefMI))
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continue;
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++NumSubstZexts;
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Changed = true;
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auto *RC = MRI->getRegClass(ZExt->getOperand(0).getReg());
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unsigned ZeroReg = MRI->createVirtualRegister(RC);
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unsigned InsertReg = MRI->createVirtualRegister(RC);
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// Initialize a register with 0. This must go before the eflags def
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BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
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ZeroReg);
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// X86 setcc only takes an output GR8, so fake a GR32 input by inserting
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// the setcc result into the low byte of the zeroed register.
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BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
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TII->get(X86::INSERT_SUBREG), InsertReg)
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.addReg(ZeroReg)
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.addReg(MI.getOperand(0).getReg())
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.addImm(X86::sub_8bit);
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MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
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ToErase.push_back(ZExt);
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}
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}
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for (auto &I : ToErase)
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I->eraseFromParent();
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return Changed;
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}

‎llvm/lib/Target/X86/X86TargetMachine.cpp

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@@ -285,7 +285,6 @@ bool X86PassConfig::addInstSelector() {
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addPass(createCleanupLocalDynamicTLSPass());
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addPass(createX86GlobalBaseRegPass());
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return false;
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}
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@@ -305,6 +304,8 @@ bool X86PassConfig::addPreISel() {
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}
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void X86PassConfig::addPreRegAlloc() {
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addPass(createX86FixupSetCC());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createX86OptimizeLEAs());
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‎llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll

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; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xorl
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define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
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entry:

‎llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll

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@@ -10,9 +10,9 @@ entry:
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; SOURCE-SCHED: subl
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; SOURCE-SCHED: movl
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; SOURCE-SCHED: sarl
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; SOURCE-SCHED: xorl
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; SOURCE-SCHED: cmpl
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; SOURCE-SCHED: setg
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; SOURCE-SCHED: movzbl
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; SOURCE-SCHED: movb
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; SOURCE-SCHED: xorl
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; SOURCE-SCHED: subl

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