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RKSimonRKSimon
committedJul 3, 2016
[X86][AVX512] Add support for masked shuffle comments
This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
·
llvmorg-21-initllvmorg-3.9.0-rc1
1 parent 129b720 commit 7c2fbdc

8 files changed

+113
-62
lines changed
 

‎llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp

+53-2
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,16 @@ using namespace llvm;
4646
CASE_AVX_INS_COMMON(Inst, Y, r##src) \
4747
CASE_SSE_INS_COMMON(Inst, r##src)
4848

49+
#define CASE_MASK_MOVDUP(Inst, src) \
50+
CASE_MASK_INS_COMMON(Inst, Z, r##src) \
51+
CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
52+
CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53+
54+
#define CASE_MASKZ_MOVDUP(Inst, src) \
55+
CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
56+
CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
57+
CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58+
4959
#define CASE_PMOVZX(Inst, src) \
5060
CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
5161
CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
@@ -129,6 +139,48 @@ static MVT getZeroExtensionResultType(const MCInst *MI) {
129139
}
130140
}
131141

142+
/// Wraps the destination register name with AVX512 mask/maskz filtering.
143+
static std::string getMaskName(const MCInst *MI, const char *DestName,
144+
const char *(*getRegName)(unsigned)) {
145+
std::string OpMaskName(DestName);
146+
147+
bool MaskWithZero = false;
148+
const char *MaskRegName = nullptr;
149+
150+
switch (MI->getOpcode()) {
151+
default:
152+
return OpMaskName;
153+
CASE_MASKZ_MOVDUP(MOVDDUP, m)
154+
CASE_MASKZ_MOVDUP(MOVDDUP, r)
155+
CASE_MASKZ_MOVDUP(MOVSHDUP, m)
156+
CASE_MASKZ_MOVDUP(MOVSHDUP, r)
157+
CASE_MASKZ_MOVDUP(MOVSLDUP, m)
158+
CASE_MASKZ_MOVDUP(MOVSLDUP, r)
159+
MaskWithZero = true;
160+
MaskRegName = getRegName(MI->getOperand(1).getReg());
161+
break;
162+
CASE_MASK_MOVDUP(MOVDDUP, m)
163+
CASE_MASK_MOVDUP(MOVDDUP, r)
164+
CASE_MASK_MOVDUP(MOVSHDUP, m)
165+
CASE_MASK_MOVDUP(MOVSHDUP, r)
166+
CASE_MASK_MOVDUP(MOVSLDUP, m)
167+
CASE_MASK_MOVDUP(MOVSLDUP, r)
168+
MaskRegName = getRegName(MI->getOperand(2).getReg());
169+
break;
170+
}
171+
172+
// MASK: zmmX {%kY}
173+
OpMaskName += " {%";
174+
OpMaskName += MaskRegName;
175+
OpMaskName += "}";
176+
177+
// MASKZ: zmmX {%kY} {z}
178+
if (MaskWithZero)
179+
OpMaskName += " {z}";
180+
181+
return OpMaskName;
182+
}
183+
132184
//===----------------------------------------------------------------------===//
133185
// Top Level Entrypoint
134186
//===----------------------------------------------------------------------===//
@@ -753,9 +805,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
753805
if (ShuffleMask.empty())
754806
return false;
755807

756-
// TODO: Add support for specifying an AVX512 style mask register in the comment.
757808
if (!DestName) DestName = Src1Name;
758-
OS << (DestName ? DestName : "mem") << " = ";
809+
OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = ";
759810

760811
// If the two sources are the same, canonicalize the input elements to be
761812
// from the first src so that we get larger element spans.

‎llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -23,13 +23,13 @@ define <8 x double> @test_mm512_mask_movddup_pd(<8 x double> %a0, i8 %a1, <8 x d
2323
; X32: # BB#0:
2424
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
2525
; X32-NEXT: kmovw %eax, %k1
26-
; X32-NEXT: vmovddup {{.*#+}} zmm0 = zmm1[0,0,2,2,4,4,6,6]
26+
; X32-NEXT: vmovddup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6]
2727
; X32-NEXT: retl
2828
;
2929
; X64-LABEL: test_mm512_mask_movddup_pd:
3030
; X64: # BB#0:
3131
; X64-NEXT: kmovw %edi, %k1
32-
; X64-NEXT: vmovddup {{.*#+}} zmm0 = zmm1[0,0,2,2,4,4,6,6]
32+
; X64-NEXT: vmovddup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6]
3333
; X64-NEXT: retq
3434
%arg1 = bitcast i8 %a1 to <8 x i1>
3535
%res0 = shufflevector <8 x double> %a2, <8 x double> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
@@ -42,13 +42,13 @@ define <8 x double> @test_mm512_maskz_movddup_pd(i8 %a0, <8 x double> %a1) {
4242
; X32: # BB#0:
4343
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
4444
; X32-NEXT: kmovw %eax, %k1
45-
; X32-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
45+
; X32-NEXT: vmovddup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6]
4646
; X32-NEXT: retl
4747
;
4848
; X64-LABEL: test_mm512_maskz_movddup_pd:
4949
; X64: # BB#0:
5050
; X64-NEXT: kmovw %edi, %k1
51-
; X64-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
51+
; X64-NEXT: vmovddup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6]
5252
; X64-NEXT: retq
5353
%arg0 = bitcast i8 %a0 to <8 x i1>
5454
%res0 = shufflevector <8 x double> %a1, <8 x double> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
@@ -75,13 +75,13 @@ define <16 x float> @test_mm512_mask_movehdup_ps(<16 x float> %a0, i16 %a1, <16
7575
; X32: # BB#0:
7676
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax
7777
; X32-NEXT: kmovw %eax, %k1
78-
; X32-NEXT: vmovshdup {{.*#+}} zmm0 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
78+
; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
7979
; X32-NEXT: retl
8080
;
8181
; X64-LABEL: test_mm512_mask_movehdup_ps:
8282
; X64: # BB#0:
8383
; X64-NEXT: kmovw %edi, %k1
84-
; X64-NEXT: vmovshdup {{.*#+}} zmm0 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
84+
; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
8585
; X64-NEXT: retq
8686
%arg1 = bitcast i16 %a1 to <16 x i1>
8787
%res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
@@ -94,13 +94,13 @@ define <16 x float> @test_mm512_maskz_movehdup_ps(i16 %a0, <16 x float> %a1) {
9494
; X32: # BB#0:
9595
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax
9696
; X32-NEXT: kmovw %eax, %k1
97-
; X32-NEXT: vmovshdup {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
97+
; X32-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
9898
; X32-NEXT: retl
9999
;
100100
; X64-LABEL: test_mm512_maskz_movehdup_ps:
101101
; X64: # BB#0:
102102
; X64-NEXT: kmovw %edi, %k1
103-
; X64-NEXT: vmovshdup {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
103+
; X64-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
104104
; X64-NEXT: retq
105105
%arg0 = bitcast i16 %a0 to <16 x i1>
106106
%res0 = shufflevector <16 x float> %a1, <16 x float> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
@@ -127,13 +127,13 @@ define <16 x float> @test_mm512_mask_moveldup_ps(<16 x float> %a0, i16 %a1, <16
127127
; X32: # BB#0:
128128
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax
129129
; X32-NEXT: kmovw %eax, %k1
130-
; X32-NEXT: vmovsldup {{.*#+}} zmm0 = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
130+
; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
131131
; X32-NEXT: retl
132132
;
133133
; X64-LABEL: test_mm512_mask_moveldup_ps:
134134
; X64: # BB#0:
135135
; X64-NEXT: kmovw %edi, %k1
136-
; X64-NEXT: vmovsldup {{.*#+}} zmm0 = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
136+
; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} = zmm1[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
137137
; X64-NEXT: retq
138138
%arg1 = bitcast i16 %a1 to <16 x i1>
139139
%res0 = shufflevector <16 x float> %a2, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
@@ -146,13 +146,13 @@ define <16 x float> @test_mm512_maskz_moveldup_ps(i16 %a0, <16 x float> %a1) {
146146
; X32: # BB#0:
147147
; X32-NEXT: movw {{[0-9]+}}(%esp), %ax
148148
; X32-NEXT: kmovw %eax, %k1
149-
; X32-NEXT: vmovsldup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
149+
; X32-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
150150
; X32-NEXT: retl
151151
;
152152
; X64-LABEL: test_mm512_maskz_moveldup_ps:
153153
; X64: # BB#0:
154154
; X64-NEXT: kmovw %edi, %k1
155-
; X64-NEXT: vmovsldup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
155+
; X64-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
156156
; X64-NEXT: retq
157157
%arg0 = bitcast i16 %a0 to <16 x i1>
158158
%res0 = shufflevector <16 x float> %a1, <16 x float> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>

‎llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll

+6-6
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ define <16 x float>@test_int_x86_avx512_mask_movsldup_512(<16 x float> %x0, <16
88
; CHECK: ## BB#0:
99
; CHECK-NEXT: vmovsldup {{.*#+}} zmm2 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
1010
; CHECK-NEXT: kmovw %edi, %k1
11-
; CHECK-NEXT: vmovsldup {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
12-
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
11+
; CHECK-NEXT: vmovsldup {{.*#+}} zmm1 {%k1} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
12+
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
1313
; CHECK-NEXT: vaddps %zmm2, %zmm1, %zmm1
1414
; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0
1515
; CHECK-NEXT: retq
@@ -28,8 +28,8 @@ define <16 x float>@test_int_x86_avx512_mask_movshdup_512(<16 x float> %x0, <16
2828
; CHECK: ## BB#0:
2929
; CHECK-NEXT: vmovshdup {{.*#+}} zmm2 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
3030
; CHECK-NEXT: kmovw %edi, %k1
31-
; CHECK-NEXT: vmovshdup {{.*#+}} zmm1 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
32-
; CHECK-NEXT: vmovshdup {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
31+
; CHECK-NEXT: vmovshdup {{.*#+}} zmm1 {%k1} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
32+
; CHECK-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
3333
; CHECK-NEXT: vaddps %zmm2, %zmm1, %zmm1
3434
; CHECK-NEXT: vaddps %zmm1, %zmm0, %zmm0
3535
; CHECK-NEXT: retq
@@ -48,8 +48,8 @@ define <8 x double>@test_int_x86_avx512_mask_movddup_512(<8 x double> %x0, <8 x
4848
; CHECK: ## BB#0:
4949
; CHECK-NEXT: vmovddup {{.*#+}} zmm2 = zmm0[0,0,2,2,4,4,6,6]
5050
; CHECK-NEXT: kmovw %edi, %k1
51-
; CHECK-NEXT: vmovddup {{.*#+}} zmm1 = zmm0[0,0,2,2,4,4,6,6]
52-
; CHECK-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
51+
; CHECK-NEXT: vmovddup {{.*#+}} zmm1 {%k1} = zmm0[0,0,2,2,4,4,6,6]
52+
; CHECK-NEXT: vmovddup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6]
5353
; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm1
5454
; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0
5555
; CHECK-NEXT: retq

‎llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

+24-24
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ define <2 x double> @test_mm_mask_movddup_pd(<2 x double> %a0, i8 %a1, <2 x doub
2929
; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
3030
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
3131
; X32-NEXT: kmovw %eax, %k1
32-
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
32+
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
3333
; X32-NEXT: popl %eax
3434
; X32-NEXT: retl
3535
;
@@ -39,7 +39,7 @@ define <2 x double> @test_mm_mask_movddup_pd(<2 x double> %a0, i8 %a1, <2 x doub
3939
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
4040
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
4141
; X64-NEXT: kmovw %eax, %k1
42-
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
42+
; X64-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
4343
; X64-NEXT: retq
4444
%trn1 = trunc i8 %a1 to i2
4545
%arg1 = bitcast i2 %trn1 to <2 x i1>
@@ -59,7 +59,7 @@ define <2 x double> @test_mm_maskz_movddup_pd(i8 %a0, <2 x double> %a1) {
5959
; X32-NEXT: movb %al, {{[0-9]+}}(%esp)
6060
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
6161
; X32-NEXT: kmovw %eax, %k1
62-
; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
62+
; X32-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
6363
; X32-NEXT: popl %eax
6464
; X32-NEXT: retl
6565
;
@@ -69,7 +69,7 @@ define <2 x double> @test_mm_maskz_movddup_pd(i8 %a0, <2 x double> %a1) {
6969
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
7070
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
7171
; X64-NEXT: kmovw %eax, %k1
72-
; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
72+
; X64-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
7373
; X64-NEXT: retq
7474
%trn1 = trunc i8 %a0 to i2
7575
%arg0 = bitcast i2 %trn1 to <2 x i1>
@@ -103,7 +103,7 @@ define <4 x double> @test_mm256_mask_movddup_pd(<4 x double> %a0, i8 %a1, <4 x d
103103
; X32-NEXT: movb %al, (%esp)
104104
; X32-NEXT: movzbl (%esp), %eax
105105
; X32-NEXT: kmovw %eax, %k1
106-
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm1[0,0,2,2]
106+
; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2]
107107
; X32-NEXT: popl %eax
108108
; X32-NEXT: retl
109109
;
@@ -113,7 +113,7 @@ define <4 x double> @test_mm256_mask_movddup_pd(<4 x double> %a0, i8 %a1, <4 x d
113113
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
114114
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
115115
; X64-NEXT: kmovw %eax, %k1
116-
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm1[0,0,2,2]
116+
; X64-NEXT: vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2]
117117
; X64-NEXT: retq
118118
%trn1 = trunc i8 %a1 to i4
119119
%arg1 = bitcast i4 %trn1 to <4 x i1>
@@ -133,7 +133,7 @@ define <4 x double> @test_mm256_maskz_movddup_pd(i8 %a0, <4 x double> %a1) {
133133
; X32-NEXT: movb %al, (%esp)
134134
; X32-NEXT: movzbl (%esp), %eax
135135
; X32-NEXT: kmovw %eax, %k1
136-
; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
136+
; X32-NEXT: vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2]
137137
; X32-NEXT: popl %eax
138138
; X32-NEXT: retl
139139
;
@@ -143,7 +143,7 @@ define <4 x double> @test_mm256_maskz_movddup_pd(i8 %a0, <4 x double> %a1) {
143143
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
144144
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
145145
; X64-NEXT: kmovw %eax, %k1
146-
; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
146+
; X64-NEXT: vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2]
147147
; X64-NEXT: retq
148148
%trn1 = trunc i8 %a0 to i4
149149
%arg0 = bitcast i4 %trn1 to <4 x i1>
@@ -177,7 +177,7 @@ define <4 x float> @test_mm_mask_movehdup_ps(<4 x float> %a0, i8 %a1, <4 x float
177177
; X32-NEXT: movb %al, (%esp)
178178
; X32-NEXT: movzbl (%esp), %eax
179179
; X32-NEXT: kmovw %eax, %k1
180-
; X32-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
180+
; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3]
181181
; X32-NEXT: popl %eax
182182
; X32-NEXT: retl
183183
;
@@ -187,7 +187,7 @@ define <4 x float> @test_mm_mask_movehdup_ps(<4 x float> %a0, i8 %a1, <4 x float
187187
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
188188
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
189189
; X64-NEXT: kmovw %eax, %k1
190-
; X64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
190+
; X64-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3]
191191
; X64-NEXT: retq
192192
%trn1 = trunc i8 %a1 to i4
193193
%arg1 = bitcast i4 %trn1 to <4 x i1>
@@ -207,7 +207,7 @@ define <4 x float> @test_mm_maskz_movehdup_ps(i8 %a0, <4 x float> %a1) {
207207
; X32-NEXT: movb %al, (%esp)
208208
; X32-NEXT: movzbl (%esp), %eax
209209
; X32-NEXT: kmovw %eax, %k1
210-
; X32-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
210+
; X32-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3]
211211
; X32-NEXT: popl %eax
212212
; X32-NEXT: retl
213213
;
@@ -217,7 +217,7 @@ define <4 x float> @test_mm_maskz_movehdup_ps(i8 %a0, <4 x float> %a1) {
217217
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
218218
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
219219
; X64-NEXT: kmovw %eax, %k1
220-
; X64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
220+
; X64-NEXT: vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3]
221221
; X64-NEXT: retq
222222
%trn0 = trunc i8 %a0 to i4
223223
%arg0 = bitcast i4 %trn0 to <4 x i1>
@@ -245,13 +245,13 @@ define <8 x float> @test_mm256_mask_movehdup_ps(<8 x float> %a0, i8 %a1, <8 x fl
245245
; X32: # BB#0:
246246
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
247247
; X32-NEXT: kmovw %eax, %k1
248-
; X32-NEXT: vmovshdup {{.*#+}} ymm0 = ymm1[1,1,3,3,5,5,7,7]
248+
; X32-NEXT: vmovshdup {{.*#+}} ymm0 {%k1} = ymm1[1,1,3,3,5,5,7,7]
249249
; X32-NEXT: retl
250250
;
251251
; X64-LABEL: test_mm256_mask_movehdup_ps:
252252
; X64: # BB#0:
253253
; X64-NEXT: kmovw %edi, %k1
254-
; X64-NEXT: vmovshdup {{.*#+}} ymm0 = ymm1[1,1,3,3,5,5,7,7]
254+
; X64-NEXT: vmovshdup {{.*#+}} ymm0 {%k1} = ymm1[1,1,3,3,5,5,7,7]
255255
; X64-NEXT: retq
256256
%arg1 = bitcast i8 %a1 to <8 x i1>
257257
%res0 = shufflevector <8 x float> %a2, <8 x float> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
@@ -264,13 +264,13 @@ define <8 x float> @test_mm256_maskz_movehdup_ps(i8 %a0, <8 x float> %a1) {
264264
; X32: # BB#0:
265265
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
266266
; X32-NEXT: kmovw %eax, %k1
267-
; X32-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
267+
; X32-NEXT: vmovshdup {{.*#+}} ymm0 {%k1} {z} = ymm0[1,1,3,3,5,5,7,7]
268268
; X32-NEXT: retl
269269
;
270270
; X64-LABEL: test_mm256_maskz_movehdup_ps:
271271
; X64: # BB#0:
272272
; X64-NEXT: kmovw %edi, %k1
273-
; X64-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7]
273+
; X64-NEXT: vmovshdup {{.*#+}} ymm0 {%k1} {z} = ymm0[1,1,3,3,5,5,7,7]
274274
; X64-NEXT: retq
275275
%arg0 = bitcast i8 %a0 to <8 x i1>
276276
%res0 = shufflevector <8 x float> %a1, <8 x float> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
@@ -303,7 +303,7 @@ define <4 x float> @test_mm_mask_moveldup_ps(<4 x float> %a0, i8 %a1, <4 x float
303303
; X32-NEXT: movb %al, (%esp)
304304
; X32-NEXT: movzbl (%esp), %eax
305305
; X32-NEXT: kmovw %eax, %k1
306-
; X32-NEXT: vmovsldup {{.*#+}} xmm0 = xmm1[0,0,2,2]
306+
; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2]
307307
; X32-NEXT: popl %eax
308308
; X32-NEXT: retl
309309
;
@@ -313,7 +313,7 @@ define <4 x float> @test_mm_mask_moveldup_ps(<4 x float> %a0, i8 %a1, <4 x float
313313
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
314314
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
315315
; X64-NEXT: kmovw %eax, %k1
316-
; X64-NEXT: vmovsldup {{.*#+}} xmm0 = xmm1[0,0,2,2]
316+
; X64-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2]
317317
; X64-NEXT: retq
318318
%trn1 = trunc i8 %a1 to i4
319319
%arg1 = bitcast i4 %trn1 to <4 x i1>
@@ -333,7 +333,7 @@ define <4 x float> @test_mm_maskz_moveldup_ps(i8 %a0, <4 x float> %a1) {
333333
; X32-NEXT: movb %al, (%esp)
334334
; X32-NEXT: movzbl (%esp), %eax
335335
; X32-NEXT: kmovw %eax, %k1
336-
; X32-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
336+
; X32-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2]
337337
; X32-NEXT: popl %eax
338338
; X32-NEXT: retl
339339
;
@@ -343,7 +343,7 @@ define <4 x float> @test_mm_maskz_moveldup_ps(i8 %a0, <4 x float> %a1) {
343343
; X64-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
344344
; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
345345
; X64-NEXT: kmovw %eax, %k1
346-
; X64-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
346+
; X64-NEXT: vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2]
347347
; X64-NEXT: retq
348348
%trn0 = trunc i8 %a0 to i4
349349
%arg0 = bitcast i4 %trn0 to <4 x i1>
@@ -371,13 +371,13 @@ define <8 x float> @test_mm256_mask_moveldup_ps(<8 x float> %a0, i8 %a1, <8 x fl
371371
; X32: # BB#0:
372372
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
373373
; X32-NEXT: kmovw %eax, %k1
374-
; X32-NEXT: vmovsldup {{.*#+}} ymm0 = ymm1[0,0,2,2,4,4,6,6]
374+
; X32-NEXT: vmovsldup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2,4,4,6,6]
375375
; X32-NEXT: retl
376376
;
377377
; X64-LABEL: test_mm256_mask_moveldup_ps:
378378
; X64: # BB#0:
379379
; X64-NEXT: kmovw %edi, %k1
380-
; X64-NEXT: vmovsldup {{.*#+}} ymm0 = ymm1[0,0,2,2,4,4,6,6]
380+
; X64-NEXT: vmovsldup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2,4,4,6,6]
381381
; X64-NEXT: retq
382382
%arg1 = bitcast i8 %a1 to <8 x i1>
383383
%res0 = shufflevector <8 x float> %a2, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
@@ -390,13 +390,13 @@ define <8 x float> @test_mm256_maskz_moveldup_ps(i8 %a0, <8 x float> %a1) {
390390
; X32: # BB#0:
391391
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
392392
; X32-NEXT: kmovw %eax, %k1
393-
; X32-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
393+
; X32-NEXT: vmovsldup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2,4,4,6,6]
394394
; X32-NEXT: retl
395395
;
396396
; X64-LABEL: test_mm256_maskz_moveldup_ps:
397397
; X64: # BB#0:
398398
; X64-NEXT: kmovw %edi, %k1
399-
; X64-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6]
399+
; X64-NEXT: vmovsldup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2,4,4,6,6]
400400
; X64-NEXT: retq
401401
%arg0 = bitcast i8 %a0 to <8 x i1>
402402
%res0 = shufflevector <8 x float> %a1, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>

‎llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,9 @@ define <4 x float>@test_int_x86_avx512_mask_movsldup_128(<4 x float> %x0, <4 x f
1010
; CHECK-NEXT: ## xmm2 = xmm0[0,0,2,2]
1111
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1212
; CHECK-NEXT: vmovsldup %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x12,0xc8]
13-
; CHECK-NEXT: ## xmm1 = xmm0[0,0,2,2]
13+
; CHECK-NEXT: ## xmm1 {%k1} = xmm0[0,0,2,2]
1414
; CHECK-NEXT: vmovsldup %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0x89,0x12,0xc0]
15-
; CHECK-NEXT: ## xmm0 = xmm0[0,0,2,2]
15+
; CHECK-NEXT: ## xmm0 {%k1} {z} = xmm0[0,0,2,2]
1616
; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x74,0x08,0x58,0xca]
1717
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7c,0x08,0x58,0xc1]
1818
; CHECK-NEXT: retq ## encoding: [0xc3]
@@ -33,9 +33,9 @@ define <8 x float>@test_int_x86_avx512_mask_movsldup_256(<8 x float> %x0, <8 x f
3333
; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2,4,4,6,6]
3434
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
3535
; CHECK-NEXT: vmovsldup %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x29,0x12,0xc8]
36-
; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2,4,4,6,6]
36+
; CHECK-NEXT: ## ymm1 {%k1} = ymm0[0,0,2,2,4,4,6,6]
3737
; CHECK-NEXT: vmovsldup %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xa9,0x12,0xc0]
38-
; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2,4,4,6,6]
38+
; CHECK-NEXT: ## ymm0 {%k1} {z} = ymm0[0,0,2,2,4,4,6,6]
3939
; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x74,0x28,0x58,0xca]
4040
; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7c,0x28,0x58,0xc1]
4141
; CHECK-NEXT: retq ## encoding: [0xc3]
@@ -56,9 +56,9 @@ define <4 x float>@test_int_x86_avx512_mask_movshdup_128(<4 x float> %x0, <4 x f
5656
; CHECK-NEXT: ## xmm2 = xmm0[1,1,3,3]
5757
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
5858
; CHECK-NEXT: vmovshdup %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x16,0xc8]
59-
; CHECK-NEXT: ## xmm1 = xmm0[1,1,3,3]
59+
; CHECK-NEXT: ## xmm1 {%k1} = xmm0[1,1,3,3]
6060
; CHECK-NEXT: vmovshdup %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0x89,0x16,0xc0]
61-
; CHECK-NEXT: ## xmm0 = xmm0[1,1,3,3]
61+
; CHECK-NEXT: ## xmm0 {%k1} {z} = xmm0[1,1,3,3]
6262
; CHECK-NEXT: vaddps %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x74,0x08,0x58,0xca]
6363
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7c,0x08,0x58,0xc1]
6464
; CHECK-NEXT: retq ## encoding: [0xc3]
@@ -79,9 +79,9 @@ define <8 x float>@test_int_x86_avx512_mask_movshdup_256(<8 x float> %x0, <8 x f
7979
; CHECK-NEXT: ## ymm2 = ymm0[1,1,3,3,5,5,7,7]
8080
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
8181
; CHECK-NEXT: vmovshdup %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7e,0x29,0x16,0xc8]
82-
; CHECK-NEXT: ## ymm1 = ymm0[1,1,3,3,5,5,7,7]
82+
; CHECK-NEXT: ## ymm1 {%k1} = ymm0[1,1,3,3,5,5,7,7]
8383
; CHECK-NEXT: vmovshdup %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xa9,0x16,0xc0]
84-
; CHECK-NEXT: ## ymm0 = ymm0[1,1,3,3,5,5,7,7]
84+
; CHECK-NEXT: ## ymm0 {%k1} {z} = ymm0[1,1,3,3,5,5,7,7]
8585
; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x74,0x28,0x58,0xca]
8686
; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7c,0x28,0x58,0xc1]
8787
; CHECK-NEXT: retq ## encoding: [0xc3]
@@ -101,9 +101,9 @@ define <2 x double>@test_int_x86_avx512_mask_movddup_128(<2 x double> %x0, <2 x
101101
; CHECK-NEXT: ## xmm2 = xmm0[0,0]
102102
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
103103
; CHECK-NEXT: vmovddup %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xff,0x09,0x12,0xc8]
104-
; CHECK-NEXT: ## xmm1 = xmm0[0,0]
104+
; CHECK-NEXT: ## xmm1 {%k1} = xmm0[0,0]
105105
; CHECK-NEXT: vmovddup %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xff,0x89,0x12,0xc0]
106-
; CHECK-NEXT: ## xmm0 = xmm0[0,0]
106+
; CHECK-NEXT: ## xmm0 {%k1} {z} = xmm0[0,0]
107107
; CHECK-NEXT: vaddpd %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0xf5,0x08,0x58,0xca]
108108
; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0x58,0xc1]
109109
; CHECK-NEXT: retq ## encoding: [0xc3]
@@ -124,9 +124,9 @@ define <4 x double>@test_int_x86_avx512_mask_movddup_256(<4 x double> %x0, <4 x
124124
; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2]
125125
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
126126
; CHECK-NEXT: vmovddup %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xff,0x29,0x12,0xc8]
127-
; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2]
127+
; CHECK-NEXT: ## ymm1 {%k1} = ymm0[0,0,2,2]
128128
; CHECK-NEXT: vmovddup %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xff,0xa9,0x12,0xc0]
129-
; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2]
129+
; CHECK-NEXT: ## ymm0 {%k1} {z} = ymm0[0,0,2,2]
130130
; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0xf5,0x28,0x58,0xca]
131131
; CHECK-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0x58,0xc1]
132132
; CHECK-NEXT: retq ## encoding: [0xc3]

‎llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ define <8 x double> @combine_vpermt2var_8f64_movddup_mask(<8 x double> %x0, <8 x
5353
; CHECK-LABEL: combine_vpermt2var_8f64_movddup_mask:
5454
; CHECK: # BB#0:
5555
; CHECK-NEXT: kmovw %edi, %k1
56-
; CHECK-NEXT: vmovddup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6]
56+
; CHECK-NEXT: vmovddup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6]
5757
; CHECK-NEXT: retq
5858
%res0 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 0, i64 0, i64 2, i64 2, i64 4, i64 4, i64 6, i64 6>, <8 x double> %x0, <8 x double> %x1, i8 %m)
5959
ret <8 x double> %res0
@@ -169,7 +169,7 @@ define <16 x float> @combine_vpermt2var_16f32_vmovshdup_mask(<16 x float> %x0, <
169169
; CHECK-LABEL: combine_vpermt2var_16f32_vmovshdup_mask:
170170
; CHECK: # BB#0:
171171
; CHECK-NEXT: kmovw %edi, %k1
172-
; CHECK-NEXT: vmovshdup {{.*#+}} zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
172+
; CHECK-NEXT: vmovshdup {{.*#+}} zmm0 {%k1} {z} = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
173173
; CHECK-NEXT: retq
174174
%res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>, <16 x float> %x0, <16 x float> %x1, i16 %m)
175175
ret <16 x float> %res0
@@ -196,7 +196,7 @@ define <16 x float> @combine_vpermt2var_16f32_vmovsldup_mask(<16 x float> %x0, <
196196
; CHECK-LABEL: combine_vpermt2var_16f32_vmovsldup_mask:
197197
; CHECK: # BB#0:
198198
; CHECK-NEXT: kmovw %edi, %k1
199-
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
199+
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
200200
; CHECK-NEXT: retq
201201
%res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>, <16 x float> %x0, <16 x float> %x1, i16 %m)
202202
ret <16 x float> %res0
@@ -205,7 +205,7 @@ define <16 x float> @combine_vpermt2var_16f32_vmovsldup_mask_load(<16 x float> *
205205
; CHECK-LABEL: combine_vpermt2var_16f32_vmovsldup_mask_load:
206206
; CHECK: # BB#0:
207207
; CHECK-NEXT: kmovw %esi, %k1
208-
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 = mem[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
208+
; CHECK-NEXT: vmovsldup {{.*#+}} zmm0 {%k1} {z} = mem[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
209209
; CHECK-NEXT: retq
210210
%x0 = load <16 x float>, <16 x float> *%p0
211211
%res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>, <16 x float> %x0, <16 x float> %x1, i16 %m)

‎llvm/utils/update_llc_test_checks.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ def llc(args, cmd_args, ir):
3232
SCRUB_TRAILING_WHITESPACE_RE = re.compile(r'[ \t]+$', flags=re.M)
3333
SCRUB_X86_SHUFFLES_RE = (
3434
re.compile(
35-
r'^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem) = .*)$',
35+
r'^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem)( \{%k\d+\}( \{z\})?)? = .*)$',
3636
flags=re.M))
3737
SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
3838
SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')

‎llvm/utils/update_test_checks.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@
4747
SCRUB_TRAILING_WHITESPACE_RE = re.compile(r'[ \t]+$', flags=re.M)
4848
SCRUB_X86_SHUFFLES_RE = (
4949
re.compile(
50-
r'^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem) = .*)$',
50+
r'^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem)( \{%k\d+\}( \{z\})?)? = .*)$',
5151
flags=re.M))
5252
SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
5353
SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')

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