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samkoltonsamkolton
committedJul 1, 2016
[AMDGPU] Assembler: support SDWA for VOPC instructions
Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 llvm-svn: 274340
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4 files changed

+176
-45
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4 files changed

+176
-45
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 30 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -724,7 +724,9 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
724724
OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
725725
void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
726726
void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
727-
void cvtSDWA(MCInst &Inst, const OperandVector &Operands, bool IsVOP1);
727+
void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
728+
void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
729+
uint64_t BasicInstType);
728730
};
729731

730732
struct OptionalOperand {
@@ -2677,15 +2679,19 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
26772679
}
26782680

26792681
void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
2680-
cvtSDWA(Inst, Operands, true);
2682+
cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
26812683
}
26822684

26832685
void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
2684-
cvtSDWA(Inst, Operands, false);
2686+
cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
2687+
}
2688+
2689+
void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
2690+
cvtSDWA(Inst, Operands, SIInstrFlags::VOPC);
26852691
}
26862692

26872693
void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
2688-
bool IsVOP1) {
2694+
uint64_t BasicInstType) {
26892695
OptionalImmIndexMap OptionalIdx;
26902696

26912697
unsigned I = 1;
@@ -2697,7 +2703,12 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
26972703
for (unsigned E = Operands.size(); I != E; ++I) {
26982704
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
26992705
// Add the register arguments
2700-
if (Op.isRegOrImmWithInputMods()) {
2706+
if (BasicInstType == SIInstrFlags::VOPC &&
2707+
Op.isReg() &&
2708+
Op.Reg.RegNo == AMDGPU::VCC) {
2709+
// VOPC sdwa use "vcc" token as dst. Skip it.
2710+
continue;
2711+
} else if (Op.isRegOrImmWithInputMods()) {
27012712
Op.addRegOrImmWithInputModsOperands(Inst, 2);
27022713
} else if (Op.isImm()) {
27032714
// Handle optional arguments
@@ -2713,15 +2724,27 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
27132724
// V_NOP_sdwa has no optional sdwa arguments
27142725
return;
27152726
}
2716-
if (IsVOP1) {
2727+
switch (BasicInstType) {
2728+
case SIInstrFlags::VOP1: {
27172729
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
27182730
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
27192731
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2720-
} else { // VOP2
2732+
break;
2733+
}
2734+
case SIInstrFlags::VOP2: {
27212735
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
27222736
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
27232737
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
27242738
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2739+
break;
2740+
}
2741+
case SIInstrFlags::VOPC: {
2742+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2743+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2744+
break;
2745+
}
2746+
default:
2747+
llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
27252748
}
27262749
}
27272750

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 79 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1253,44 +1253,56 @@ class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
12531253
}
12541254

12551255
class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
1256-
bit HasFloatModifiers> {
1257-
1258-
dag ret = !if (!eq(NumSrcArgs, 0),
1259-
// VOP1 without input operands (V_NOP)
1260-
(ins),
1261-
!if (!eq(NumSrcArgs, 1),
1262-
!if (HasFloatModifiers,
1263-
// VOP1_SDWA with float modifiers
1264-
(ins FPInputMods:$src0_fmodifiers, Src0RC:$src0,
1265-
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1266-
src0_sel:$src0_sel)
1267-
/* else */,
1268-
// VOP1_SDWA with sext modifier
1269-
(ins IntInputMods:$src0_imodifiers, Src0RC:$src0,
1270-
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1271-
src0_sel:$src0_sel)
1272-
/* endif */)
1256+
bit HasFloatModifiers, ValueType DstVT> {
1257+
1258+
dag ret = !if(!eq(NumSrcArgs, 0),
1259+
// VOP1 without input operands (V_NOP)
1260+
(ins),
1261+
!if(!eq(NumSrcArgs, 1),
1262+
!if(HasFloatModifiers,
1263+
// VOP1_SDWA with float modifiers
1264+
(ins FPInputMods:$src0_fmodifiers, Src0RC:$src0,
1265+
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1266+
src0_sel:$src0_sel)
1267+
/* else */,
1268+
// VOP1_SDWA with sext modifier
1269+
(ins IntInputMods:$src0_imodifiers, Src0RC:$src0,
1270+
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1271+
src0_sel:$src0_sel)
1272+
/* endif */)
12731273
/* NumSrcArgs == 2 */,
1274-
!if (HasFloatModifiers,
1275-
// VOP2_SDWA with float modifiers
1276-
(ins FPInputMods:$src0_fmodifiers, Src0RC:$src0,
1277-
FPInputMods:$src1_fmodifiers, Src1RC:$src1,
1278-
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1279-
src0_sel:$src0_sel, src1_sel:$src1_sel)
1280-
/* else */,
1281-
// VOP2_DPP with sext modifier
1282-
(ins IntInputMods:$src0_imodifiers, Src0RC:$src0,
1283-
IntInputMods:$src1_imodifiers, Src1RC:$src1,
1284-
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1285-
src0_sel:$src0_sel, src1_sel:$src1_sel)
1274+
!if(HasFloatModifiers,
1275+
!if(!eq(DstVT.Size, 1),
1276+
// VOPC_SDWA with float modifiers
1277+
(ins FPInputMods:$src0_fmodifiers, Src0RC:$src0,
1278+
FPInputMods:$src1_fmodifiers, Src1RC:$src1,
1279+
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1280+
// VOP2_SDWA or VOPC_SDWA with float modifiers
1281+
(ins FPInputMods:$src0_fmodifiers, Src0RC:$src0,
1282+
FPInputMods:$src1_fmodifiers, Src1RC:$src1,
1283+
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1284+
src0_sel:$src0_sel, src1_sel:$src1_sel)
1285+
),
1286+
/* else */
1287+
!if(!eq(DstVT.Size, 1),
1288+
// VOPC_SDWA with sext modifiers
1289+
(ins IntInputMods:$src0_imodifiers, Src0RC:$src0,
1290+
IntInputMods:$src1_imodifiers, Src1RC:$src1,
1291+
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1292+
// VOP2_SDWA or VOPC_SDWA with sext modifier
1293+
(ins IntInputMods:$src0_imodifiers, Src0RC:$src0,
1294+
IntInputMods:$src1_imodifiers, Src1RC:$src1,
1295+
clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
1296+
src0_sel:$src0_sel, src1_sel:$src1_sel)
1297+
)
12861298
/* endif */)));
12871299
}
12881300

12891301
// Outs for DPP and SDWA
12901302
class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
12911303
dag ret = !if(HasDst,
12921304
!if(!eq(DstVT.Size, 1),
1293-
(outs DstRCDPP:$sdst), // sdst for VOPC
1305+
(outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
12941306
(outs DstRCDPP:$vdst)),
12951307
(outs)); // V_NOP
12961308
}
@@ -1344,7 +1356,7 @@ class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasFloatModifiers,
13441356
ValueType DstVT = i32> {
13451357
string dst = !if(HasDst,
13461358
!if(!eq(DstVT.Size, 1),
1347-
"$sdst", // use $sdst for VOPC
1359+
" vcc", // use vcc token as dst for VOPC instructioins
13481360
"$vdst"),
13491361
"");
13501362
string src0 = !if(HasFloatModifiers, "$src0_fmodifiers", "$src0_imodifiers");
@@ -1360,7 +1372,10 @@ class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasFloatModifiers,
13601372
"",
13611373
!if(!eq(NumSrcArgs, 1),
13621374
" $dst_sel $dst_unused $src0_sel",
1363-
" $dst_sel $dst_unused $src0_sel $src1_sel"
1375+
!if(!eq(DstVT.Size, 1),
1376+
" $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1377+
" $dst_sel $dst_unused $src0_sel $src1_sel"
1378+
)
13641379
)
13651380
);
13661381
string ret = dst#args#sdwa;
@@ -1425,7 +1440,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
14251440
field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
14261441
HasModifiers>.ret;
14271442
field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs, HasModifiers>.ret;
1428-
field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs, HasModifiers>.ret;
1443+
field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs, HasModifiers, DstVT>.ret;
14291444

14301445
field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
14311446
field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
@@ -1538,6 +1553,11 @@ class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, v
15381553
class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
15391554
let Ins64 = (ins FPInputMods:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
15401555
let Asm64 = "$sdst, $src0_modifiers, $src1";
1556+
let InsSDWA = (ins FPInputMods:$src0_fmodifiers, Src0RC64:$src0,
1557+
IntInputMods:$src1_imodifiers, Src1RC64:$src1,
1558+
clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
1559+
let AsmSDWA = " vcc, $src0_fmodifiers, $src1_imodifiers$clamp $src0_sel $src1_sel";
1560+
15411561
}
15421562

15431563
def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
@@ -2247,6 +2267,18 @@ class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
22472267
let isCodeGenOnly = 1;
22482268
}
22492269

2270+
class VOPC_SDWA <vopc op, string opName, bit DefExec, VOPProfile p> :
2271+
VOPC_SDWAe <op.VI>,
2272+
VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>,
2273+
SDWADisableFields <p> {
2274+
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
2275+
let hasSideEffects = DefExec;
2276+
let AsmMatchConverter = "cvtSdwaVOPC";
2277+
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
2278+
let DecoderNamespace = "SDWA";
2279+
let DisableDecoder = DisableVIDecoder;
2280+
}
2281+
22502282
multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
22512283
string opName, bit DefExec, VOPProfile p,
22522284
list<SchedReadWrite> sched,
@@ -2293,6 +2325,8 @@ multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
22932325

22942326
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
22952327
opName, p.HasModifiers, DefExec, revOp, sched>;
2328+
2329+
def _sdwa : VOPC_SDWA <op, opName, DefExec, p>;
22962330
}
22972331

22982332
// Special case for class instructions which only have modifiers on
@@ -2305,6 +2339,11 @@ multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
23052339
defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
23062340
opName, p.HasModifiers, DefExec, revOp, sched>,
23072341
VOP3DisableModFields<1, 0, 0>;
2342+
2343+
def _sdwa : VOPC_SDWA <op, opName, DefExec, p> {
2344+
let src1_fmodifiers = 0;
2345+
let src1_imodifiers = ?;
2346+
}
23082347
}
23092348

23102349
multiclass VOPCInst <vopc op, string opName,
@@ -2367,11 +2406,6 @@ multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
23672406
multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
23682407
VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>;
23692408

2370-
multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
2371-
list<dag> pat, int NumSrcArgs, bit HasMods,
2372-
bit VOP3Only = 0> : VOP3_m <
2373-
op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods, VOP3Only
2374-
>;
23752409

23762410
multiclass VOPC_CLASS_F32 <vopc op, string opName> :
23772411
VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>;
@@ -2385,6 +2419,13 @@ multiclass VOPC_CLASS_F64 <vopc op, string opName> :
23852419
multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
23862420
VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
23872421

2422+
2423+
multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
2424+
list<dag> pat, int NumSrcArgs, bit HasMods,
2425+
bit VOP3Only = 0> : VOP3_m <
2426+
op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods, VOP3Only
2427+
>;
2428+
23882429
multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
23892430
SDPatternOperator node = null_frag, bit VOP3Only = 0> :
23902431
VOP3_Helper <

‎llvm/lib/Target/AMDGPU/VIInstrFormats.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -282,6 +282,10 @@ class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
282282
let Inst{16-9} = src1;
283283
let Inst{24-17} = op;
284284
let Inst{31-25} = 0x3e; // encoding
285+
286+
// VOPC disallows dst_sel and dst_unused as they have no effect on destination
287+
let Inst{42-40} = 0x6;
288+
let Inst{44-43} = 0x2;
285289
}
286290

287291
class EXPe_vi : EXPe {

‎llvm/test/MC/AMDGPU/vop_sdwa.s

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,10 @@ v_mov_b32_sdwa v1, sext(v0)
112112
// VI: v_and_b32_sdwa v0, sext(v0), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x26,0x00,0x06,0x0e,0x0a]
113113
v_and_b32 v0, sext(v0), sext(v0) dst_unused:UNUSED_PAD src1_sel:BYTE_2
114114

115+
// NOSICI: error:
116+
// VI: v_cmp_class_f32 vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x16,0x12,0x0c]
117+
v_cmp_class_f32 vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0
118+
115119
//===----------------------------------------------------------------------===//
116120
// Check VOP1 opcodes
117121
//===----------------------------------------------------------------------===//
@@ -496,3 +500,62 @@ v_min_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_se
496500
// VI: v_ldexp_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x66,0x02,0x06,0x05,0x02]
497501
v_ldexp_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
498502

503+
//===----------------------------------------------------------------------===//
504+
// Check VOPC opcodes
505+
//===----------------------------------------------------------------------===//
506+
507+
// NOSICI: error:
508+
// VI: v_cmp_eq_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x16,0x02,0x04]
509+
v_cmp_eq_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
510+
511+
// NOSICI: error:
512+
// VI: v_cmp_nle_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7c,0x01,0x16,0x02,0x04]
513+
v_cmp_nle_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
514+
515+
// NOSICI: error:
516+
// VI: v_cmpx_gt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa8,0x7c,0x01,0x16,0x02,0x04]
517+
v_cmpx_gt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
518+
519+
// NOSICI: error:
520+
// VI: v_cmpx_nlt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xbc,0x7c,0x01,0x16,0x02,0x04]
521+
v_cmpx_nlt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
522+
523+
// NOSICI: error:
524+
// VI: v_cmp_lt_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x82,0x7d,0x01,0x16,0x02,0x04]
525+
v_cmp_lt_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
526+
527+
// NOSICI: error:
528+
// VI: v_cmp_t_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x16,0x02,0x04]
529+
v_cmp_t_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
530+
531+
// NOSICI: error:
532+
// VI: v_cmpx_eq_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x16,0x02,0x04]
533+
v_cmpx_eq_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
534+
535+
// NOSICI: error:
536+
// VI: v_cmpx_ne_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x16,0x02,0x04]
537+
v_cmpx_ne_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
538+
539+
// NOSICI: error:
540+
// VI: v_cmp_f_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x90,0x7d,0x01,0x16,0x02,0x04]
541+
v_cmp_f_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
542+
543+
// NOSICI: error:
544+
// VI: v_cmp_gt_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7d,0x01,0x16,0x02,0x04]
545+
v_cmp_gt_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
546+
547+
// NOSICI: error:
548+
// VI: v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x16,0x02,0x04]
549+
v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
550+
551+
// NOSICI: error:
552+
// VI: v_cmpx_ne_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xba,0x7d,0x01,0x16,0x02,0x04]
553+
v_cmpx_ne_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
554+
555+
// NOSICI: error:
556+
// VI: v_cmp_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x16,0x02,0x04]
557+
v_cmp_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
558+
559+
// NOSICI: error:
560+
// VI: v_cmpx_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x16,0x02,0x04]
561+
v_cmpx_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0

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