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RKSimonRKSimon
committedMay 4, 2016
[SelectionDAG] BITREVERSE vector legalization of bit operations
Vector bit operations are typically promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use isOperationLegalOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268504
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‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

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@@ -894,8 +894,8 @@ SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
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// than unrolling and expanding each component.
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if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::OR, VT))
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!TLI.isOperationLegalOrPromote(ISD::AND, VT) ||
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!TLI.isOperationLegalOrPromote(ISD::OR, VT))
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return DAG.UnrollVectorOp(Op.getNode());
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// Let LegalizeDAG handle this later.

‎llvm/test/CodeGen/X86/vector-bitreverse.ll

Lines changed: 2082 additions & 12528 deletions
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