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manman-renmanman-ren
committedApr 11, 2016
Swift Calling Convention: swifterror target support.
Differential Revision: http://reviews.llvm.org/D18716 llvm-svn: 265997
1 parent 2fec729 commit 5751814

17 files changed

+1344
-7
lines changed
 

Diff for: ‎llvm/lib/Target/AArch64/AArch64CallingConvention.td

+8
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,8 @@ def RetCC_AArch64_AAPCS : CallingConv<[
8686
CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
8787
CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
8888

89+
CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X19], [W19]>>>,
90+
8991
// Big endian vectors must be passed as if they were 1-element vectors so that
9092
// their lanes are in a consistent order.
9193
CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
@@ -129,6 +131,9 @@ def CC_AArch64_DarwinPCS : CallingConv<[
129131
// A SwiftSelf is passed in X9.
130132
CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X9], [W9]>>>,
131133

134+
// A SwiftError is passed in X19.
135+
CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X19], [W19]>>>,
136+
132137
CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
133138

134139
// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
@@ -273,6 +278,9 @@ def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
273278
// case)
274279
def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
275280

281+
def CSR_AArch64_AAPCS_SwiftError
282+
: CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X19)>;
283+
276284
// The function used by Darwin to obtain the address of a thread-local variable
277285
// guarantees more than a normal AAPCS function. x16 and x17 are used on the
278286
// fast path for calculation, but other registers except X0 (argument/return)

Diff for: ‎llvm/lib/Target/AArch64/AArch64FastISel.cpp

+36-1
Original file line numberDiff line numberDiff line change
@@ -1900,6 +1900,21 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
19001900
cast<LoadInst>(I)->isAtomic())
19011901
return false;
19021902

1903+
const Value *SV = I->getOperand(0);
1904+
if (TLI.supportSwiftError()) {
1905+
// Swifterror values can come from either a function parameter with
1906+
// swifterror attribute or an alloca with swifterror attribute.
1907+
if (const Argument *Arg = dyn_cast<Argument>(SV)) {
1908+
if (Arg->hasSwiftErrorAttr())
1909+
return false;
1910+
}
1911+
1912+
if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
1913+
if (Alloca->isSwiftError())
1914+
return false;
1915+
}
1916+
}
1917+
19031918
// See if we can handle this address.
19041919
Address Addr;
19051920
if (!computeAddress(I->getOperand(0), Addr, I->getType()))
@@ -2064,6 +2079,21 @@ bool AArch64FastISel::selectStore(const Instruction *I) {
20642079
cast<StoreInst>(I)->isAtomic())
20652080
return false;
20662081

2082+
const Value *PtrV = I->getOperand(1);
2083+
if (TLI.supportSwiftError()) {
2084+
// Swifterror values can come from either a function parameter with
2085+
// swifterror attribute or an alloca with swifterror attribute.
2086+
if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
2087+
if (Arg->hasSwiftErrorAttr())
2088+
return false;
2089+
}
2090+
2091+
if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
2092+
if (Alloca->isSwiftError())
2093+
return false;
2094+
}
2095+
}
2096+
20672097
// Get the value to be stored into a register. Use the zero register directly
20682098
// when possible to avoid an unnecessary copy and a wasted register.
20692099
unsigned SrcReg = 0;
@@ -2810,6 +2840,7 @@ bool AArch64FastISel::fastLowerArguments() {
28102840
F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
28112841
F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
28122842
F->getAttributes().hasAttribute(Idx, Attribute::SwiftSelf) ||
2843+
F->getAttributes().hasAttribute(Idx, Attribute::SwiftError) ||
28132844
F->getAttributes().hasAttribute(Idx, Attribute::Nest))
28142845
return false;
28152846

@@ -3062,7 +3093,7 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
30623093

30633094
for (auto Flag : CLI.OutFlags)
30643095
if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() ||
3065-
Flag.isSwiftSelf())
3096+
Flag.isSwiftSelf() || Flag.isSwiftError())
30663097
return false;
30673098

30683099
// Set up the argument vectors.
@@ -3644,6 +3675,10 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
36443675
if (F.isVarArg())
36453676
return false;
36463677

3678+
if (TLI.supportSwiftError() &&
3679+
F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
3680+
return false;
3681+
36473682
if (TLI.supportSplitCSR(FuncInfo.MF))
36483683
return false;
36493684

Diff for: ‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

+13-5
Original file line numberDiff line numberDiff line change
@@ -706,6 +706,15 @@ static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
706706
return getKillRegState(LRKill);
707707
}
708708

709+
static bool produceCompactUnwindFrame(MachineFunction &MF) {
710+
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
711+
AttributeSet Attrs = MF.getFunction()->getAttributes();
712+
return Subtarget.isTargetMachO() &&
713+
!(Subtarget.getTargetLowering()->supportSwiftError() &&
714+
Attrs.hasAttrSomewhere(Attribute::SwiftError));
715+
}
716+
717+
709718
struct RegPairInfo {
710719
RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {}
711720
unsigned Reg1;
@@ -730,7 +739,7 @@ static void computeCalleeSaveRegisterPairs(
730739
(void)CC;
731740
// MachO's compact unwind format relies on all registers being stored in
732741
// pairs.
733-
assert((!MF.getSubtarget<AArch64Subtarget>().isTargetMachO() ||
742+
assert((!produceCompactUnwindFrame(MF) ||
734743
CC == CallingConv::PreserveMost ||
735744
(Count & 1) == 0) &&
736745
"Odd number of callee-saved regs to spill!");
@@ -764,7 +773,7 @@ static void computeCalleeSaveRegisterPairs(
764773

765774
// MachO's compact unwind format relies on all registers being stored in
766775
// adjacent register pairs.
767-
assert((!MF.getSubtarget<AArch64Subtarget>().isTargetMachO() ||
776+
assert((!produceCompactUnwindFrame(MF) ||
768777
CC == CallingConv::PreserveMost ||
769778
(RPI.isPaired() &&
770779
((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
@@ -954,7 +963,6 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
954963
const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
955964
MF.getSubtarget().getRegisterInfo());
956965
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
957-
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
958966
unsigned UnspilledCSGPR = AArch64::NoRegister;
959967
unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
960968

@@ -992,7 +1000,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
9921000
// MachO's compact unwind format relies on all registers being stored in
9931001
// pairs.
9941002
// FIXME: the usual format is actually better if unwinding isn't needed.
995-
if (Subtarget.isTargetMachO() && !SavedRegs.test(PairedReg)) {
1003+
if (produceCompactUnwindFrame(MF) && !SavedRegs.test(PairedReg)) {
9961004
SavedRegs.set(PairedReg);
9971005
ExtraCSSpill = true;
9981006
}
@@ -1035,7 +1043,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
10351043
// MachO's compact unwind format relies on all registers being stored in
10361044
// pairs, so if we need to spill one extra for BigStack, then we need to
10371045
// store the pair.
1038-
if (Subtarget.isTargetMachO())
1046+
if (produceCompactUnwindFrame(MF))
10391047
SavedRegs.set(UnspilledCSGPRPaired);
10401048
ExtraCSSpill = true;
10411049
NumRegsSpilled = SavedRegs.count();

Diff for: ‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

+4
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,10 @@ class AArch64TargetLowering : public TargetLowering {
400400
MachineBasicBlock *Entry,
401401
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
402402

403+
bool supportSwiftError() const override {
404+
return true;
405+
}
406+
403407
private:
404408
bool isExtFreeImpl(const Instruction *Ext) const override;
405409

Diff for: ‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

+9
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,11 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
5151
return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
5252
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
5353
CSR_AArch64_CXX_TLS_Darwin_SaveList;
54+
if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
55+
->supportSwiftError() &&
56+
MF->getFunction()->getAttributes().hasAttrSomewhere(
57+
Attribute::SwiftError))
58+
return CSR_AArch64_AAPCS_SwiftError_SaveList;
5459
if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)
5560
return CSR_AArch64_RT_MostRegs_SaveList;
5661
else
@@ -76,6 +81,10 @@ AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
7681
return CSR_AArch64_AllRegs_RegMask;
7782
if (CC == CallingConv::CXX_FAST_TLS)
7883
return CSR_AArch64_CXX_TLS_Darwin_RegMask;
84+
if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
85+
->supportSwiftError() &&
86+
MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
87+
return CSR_AArch64_AAPCS_SwiftError_RegMask;
7988
if (CC == CallingConv::PreserveMost)
8089
return CSR_AArch64_RT_MostRegs_RegMask;
8190
else

Diff for: ‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

+9
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,10 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
8787
}
8888
}
8989

90+
if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
91+
F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
92+
return CSR_iOS_SwiftError_SaveList;
93+
9094
if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
9195
return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
9296
? CSR_iOS_CXX_TLS_PE_SaveList
@@ -110,6 +114,11 @@ ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
110114
if (CC == CallingConv::GHC)
111115
// This is academic becase all GHC calls are (supposed to be) tail calls
112116
return CSR_NoRegs_RegMask;
117+
118+
if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
119+
MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
120+
return CSR_iOS_SwiftError_RegMask;
121+
113122
if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
114123
return CSR_iOS_CXX_TLS_RegMask;
115124
return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;

Diff for: ‎llvm/lib/Target/ARM/ARMCallingConv.td

+21
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,9 @@ def CC_ARM_APCS : CallingConv<[
2626
// A SwiftSelf is passed in R9.
2727
CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R9]>>>,
2828

29+
// A SwiftError is passed in R6.
30+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
31+
2932
// Handle all vector types as either f64 or v2f64.
3033
CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
3134
CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
@@ -45,6 +48,9 @@ def RetCC_ARM_APCS : CallingConv<[
4548
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
4649
CCIfType<[f32], CCBitConvertToType<i32>>,
4750

51+
// A SwiftError is returned in R6.
52+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
53+
4854
// Handle all vector types as either f64 or v2f64.
4955
CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
5056
CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
@@ -157,6 +163,9 @@ def CC_ARM_AAPCS : CallingConv<[
157163
// A SwiftSelf is passed in R9.
158164
CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R9]>>>,
159165

166+
// A SwiftError is passed in R6.
167+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
168+
160169
CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
161170
CCIfType<[f32], CCBitConvertToType<i32>>,
162171
CCDelegateTo<CC_ARM_AAPCS_Common>
@@ -167,6 +176,9 @@ def RetCC_ARM_AAPCS : CallingConv<[
167176
CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
168177
CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169178

179+
// A SwiftError is returned in R6.
180+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
181+
170182
CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
171183
CCIfType<[f32], CCBitConvertToType<i32>>,
172184
CCDelegateTo<RetCC_ARM_AAPCS_Common>
@@ -188,6 +200,9 @@ def CC_ARM_AAPCS_VFP : CallingConv<[
188200
// A SwiftSelf is passed in R9.
189201
CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R9]>>>,
190202

203+
// A SwiftError is passed in R6.
204+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
205+
191206
// HFAs are passed in a contiguous block of registers, or on the stack
192207
CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
193208

@@ -203,6 +218,9 @@ def RetCC_ARM_AAPCS_VFP : CallingConv<[
203218
CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
204219
CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
205220

221+
// A SwiftError is returned in R6.
222+
CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
223+
206224
CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
207225
CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
208226
CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
@@ -231,6 +249,9 @@ def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
231249
// Also save R7-R4 first to match the stack frame fixed spill areas.
232250
def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
233251

252+
// R6 is used to pass swifterror, remove it from CSR.
253+
def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R6)>;
254+
234255
def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
235256
(sub CSR_AAPCS_ThisReturn, R9))>;
236257

Diff for: ‎llvm/lib/Target/ARM/ARMFastISel.cpp

+36
Original file line numberDiff line numberDiff line change
@@ -1062,6 +1062,21 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
10621062
if (cast<LoadInst>(I)->isAtomic())
10631063
return false;
10641064

1065+
const Value *SV = I->getOperand(0);
1066+
if (TLI.supportSwiftError()) {
1067+
// Swifterror values can come from either a function parameter with
1068+
// swifterror attribute or an alloca with swifterror attribute.
1069+
if (const Argument *Arg = dyn_cast<Argument>(SV)) {
1070+
if (Arg->hasSwiftErrorAttr())
1071+
return false;
1072+
}
1073+
1074+
if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
1075+
if (Alloca->isSwiftError())
1076+
return false;
1077+
}
1078+
}
1079+
10651080
// Verify we have a legal type before going any further.
10661081
MVT VT;
10671082
if (!isLoadTypeLegal(I->getType(), VT))
@@ -1177,6 +1192,21 @@ bool ARMFastISel::SelectStore(const Instruction *I) {
11771192
if (cast<StoreInst>(I)->isAtomic())
11781193
return false;
11791194

1195+
const Value *PtrV = I->getOperand(1);
1196+
if (TLI.supportSwiftError()) {
1197+
// Swifterror values can come from either a function parameter with
1198+
// swifterror attribute or an alloca with swifterror attribute.
1199+
if (const Argument *Arg = dyn_cast<Argument>(PtrV)) {
1200+
if (Arg->hasSwiftErrorAttr())
1201+
return false;
1202+
}
1203+
1204+
if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
1205+
if (Alloca->isSwiftError())
1206+
return false;
1207+
}
1208+
}
1209+
11801210
// Verify we have a legal type before going any further.
11811211
MVT VT;
11821212
if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
@@ -2085,6 +2115,10 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
20852115
if (!FuncInfo.CanLowerReturn)
20862116
return false;
20872117

2118+
if (TLI.supportSwiftError() &&
2119+
F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2120+
return false;
2121+
20882122
if (TLI.supportSplitCSR(FuncInfo.MF))
20892123
return false;
20902124

@@ -2347,6 +2381,7 @@ bool ARMFastISel::SelectCall(const Instruction *I,
23472381
if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
23482382
CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
23492383
CS.paramHasAttr(AttrInd, Attribute::SwiftSelf) ||
2384+
CS.paramHasAttr(AttrInd, Attribute::SwiftError) ||
23502385
CS.paramHasAttr(AttrInd, Attribute::Nest) ||
23512386
CS.paramHasAttr(AttrInd, Attribute::ByVal))
23522387
return false;
@@ -3023,6 +3058,7 @@ bool ARMFastISel::fastLowerArguments() {
30233058
if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
30243059
F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
30253060
F->getAttributes().hasAttribute(Idx, Attribute::SwiftSelf) ||
3061+
F->getAttributes().hasAttribute(Idx, Attribute::SwiftError) ||
30263062
F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
30273063
return false;
30283064

Diff for: ‎llvm/lib/Target/ARM/ARMISelLowering.h

+4
Original file line numberDiff line numberDiff line change
@@ -470,6 +470,10 @@ namespace llvm {
470470
bool isCheapToSpeculateCttz() const override;
471471
bool isCheapToSpeculateCtlz() const override;
472472

473+
bool supportSwiftError() const override {
474+
return true;
475+
}
476+
473477
protected:
474478
std::pair<const TargetRegisterClass *, uint8_t>
475479
findRepresentativeClass(const TargetRegisterInfo *TRI,

Diff for: ‎llvm/lib/Target/X86/X86CallingConv.td

+8
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,9 @@ def RetCC_X86_64_C : CallingConv<[
162162

163163
// MMX vector types are always returned in XMM0.
164164
CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
165+
166+
CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
167+
165168
CCDelegateTo<RetCC_X86Common>
166169
]>;
167170

@@ -297,6 +300,9 @@ def CC_X86_64_C : CallingConv<[
297300
// A SwiftSelf is passed in R10.
298301
CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10]>>>,
299302

303+
// A SwiftError is passed in R12.
304+
CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
305+
300306
// The first 6 integer arguments are passed in integer registers.
301307
CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
302308
CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
@@ -845,6 +851,8 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>;
845851
def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
846852
def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
847853

854+
def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
855+
848856
def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
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def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
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