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author
Elena Demikhovsky
committedJan 24, 2016
Added Skylake client to X86 targets and features
Changes in X86.td: I set features of Intel processors in incremental form: IVB = SNB + X HSW = IVB + X .. I added Skylake client processor and defined it's features FeatureADX was missing on KNL Added some new features to appropriate processors SMAP, IFMA, PREFETCHWT1, VMFUNC and others Differential Revision: http://reviews.llvm.org/D16357 llvm-svn: 258659
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6 files changed

+337
-199
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6 files changed

+337
-199
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‎llvm/lib/Support/Host.cpp

+12-3
Original file line numberDiff line numberDiff line change
@@ -805,25 +805,34 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
805805
Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
806806

807807
Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
808+
Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
808809
Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
809810
Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
810811
Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
812+
Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
811813
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
812814
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
813815
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
816+
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
817+
Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
818+
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
819+
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
814820
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
815-
// Enable protection keys
816-
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
817821

818822
// AVX512 is only supported if the OS supports the context save for it.
819823
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
820824
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
825+
Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
821826
Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
822827
Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
823828
Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
824829
Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
825830
Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
826-
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
831+
832+
Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
833+
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
834+
// Enable protection keys
835+
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
827836

828837
bool HasLeafD = MaxLevel >= 0xd &&
829838
!GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);

‎llvm/lib/Target/X86/X86.td

+95-138
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,9 @@ def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
125125
def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
126126
"Enable AVX-512 PreFetch Instructions",
127127
[FeatureAVX512]>;
128+
def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
129+
"true",
130+
"Prefetch with Intent to Write and T1 Hint">;
128131
def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
129132
"Enable AVX-512 Doubleword and Quadword Instructions",
130133
[FeatureAVX512]>;
@@ -137,6 +140,9 @@ def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
137140
def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
138141
"Enable AVX-512 Vector Bit Manipulation Instructions",
139142
[FeatureAVX512]>;
143+
def FeatureIFMA : SubtargetFeature<"ifma", "HasIFMA", "true",
144+
"Enable AVX-512 Integer Fused Multiple-Add",
145+
[FeatureAVX512]>;
140146
def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
141147
"Enable protection keys">;
142148
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
@@ -202,6 +208,20 @@ def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
202208
def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
203209
"PadShortFunctions", "true",
204210
"Pad short functions">;
211+
def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
212+
"Invalidate Process-Context Identifier">;
213+
def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
214+
"VM Functions">;
215+
def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
216+
"Supervisor Mode Access Protection">;
217+
def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
218+
"Enable Software Guard Extensions">;
219+
def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
220+
"Flush A Cache Line Optimized">;
221+
def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
222+
"Enable Persistent Commit">;
223+
def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
224+
"Cache Line Write Back">;
205225
// TODO: This feature ought to be renamed.
206226
// What it really refers to are CPUs for which certain instructions
207227
// (which ones besides the example below?) are microcoded.
@@ -365,201 +385,138 @@ def : WestmereProc<"westmere">;
365385

366386
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
367387
// rather than a superset.
368-
class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
388+
def ProcIntelSNB : SubtargetFeature<"snb", "X86ProcFamily", "IntelSNB",
389+
" Intel SandyBridge Processor", [
369390
FeatureMMX,
370391
FeatureAVX,
371392
FeatureFXSR,
372393
FeatureCMPXCHG16B,
373-
FeatureSlowBTMem,
374-
FeatureSlowUAMem32,
375394
FeaturePOPCNT,
376395
FeatureAES,
377396
FeaturePCLMUL,
378397
FeatureXSAVE,
379398
FeatureXSAVEOPT,
380399
FeatureLAHFSAHF
381400
]>;
401+
402+
class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
403+
ProcIntelSNB,
404+
FeatureSlowBTMem,
405+
FeatureSlowUAMem32
406+
]>;
382407
def : SandyBridgeProc<"sandybridge">;
383408
def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
384409

385-
class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
386-
FeatureMMX,
387-
FeatureAVX,
388-
FeatureFXSR,
389-
FeatureCMPXCHG16B,
390-
FeatureSlowBTMem,
391-
FeatureSlowUAMem32,
392-
FeaturePOPCNT,
393-
FeatureAES,
394-
FeaturePCLMUL,
395-
FeatureXSAVE,
396-
FeatureXSAVEOPT,
410+
def ProcIntelIVB : SubtargetFeature<"ivb", "X86ProcFamily", "IntelIVB",
411+
" Intel IvyBridge Processor", [
412+
ProcIntelSNB,
397413
FeatureRDRAND,
398414
FeatureF16C,
399-
FeatureFSGSBase,
400-
FeatureLAHFSAHF
415+
FeatureFSGSBase
416+
]>;
417+
418+
class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
419+
ProcIntelIVB,
420+
FeatureSlowBTMem,
421+
FeatureSlowUAMem32
401422
]>;
402423
def : IvyBridgeProc<"ivybridge">;
403424
def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
404425

405-
class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
406-
FeatureMMX,
426+
def ProcIntelHSW : SubtargetFeature<"hsw", "X86ProcFamily", "IntelHSW",
427+
" Intel Haswell Processor", [
428+
ProcIntelIVB,
407429
FeatureAVX2,
408-
FeatureFXSR,
409-
FeatureCMPXCHG16B,
410-
FeatureSlowBTMem,
411-
FeaturePOPCNT,
412-
FeatureAES,
413-
FeaturePCLMUL,
414-
FeatureRDRAND,
415-
FeatureXSAVE,
416-
FeatureXSAVEOPT,
417-
FeatureF16C,
418-
FeatureFSGSBase,
419-
FeatureMOVBE,
420-
FeatureLZCNT,
421430
FeatureBMI,
422431
FeatureBMI2,
423432
FeatureFMA,
433+
FeatureLZCNT,
434+
FeatureMOVBE,
435+
FeatureINVPCID,
436+
FeatureVMFUNC,
424437
FeatureRTM,
425438
FeatureHLE,
426-
FeatureSlowIncDec,
427-
FeatureLAHFSAHF
439+
FeatureSlowIncDec
428440
]>;
441+
442+
class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel,
443+
[ProcIntelHSW]>;
429444
def : HaswellProc<"haswell">;
430445
def : HaswellProc<"core-avx2">; // Legacy alias.
431446

432-
class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
433-
FeatureMMX,
434-
FeatureAVX2,
435-
FeatureFXSR,
436-
FeatureCMPXCHG16B,
437-
FeatureSlowBTMem,
438-
FeaturePOPCNT,
439-
FeatureAES,
440-
FeaturePCLMUL,
441-
FeatureXSAVE,
442-
FeatureXSAVEOPT,
443-
FeatureRDRAND,
444-
FeatureF16C,
445-
FeatureFSGSBase,
446-
FeatureMOVBE,
447-
FeatureLZCNT,
448-
FeatureBMI,
449-
FeatureBMI2,
450-
FeatureFMA,
451-
FeatureRTM,
452-
FeatureHLE,
447+
def ProcIntelBDW : SubtargetFeature<"bdw", "X86ProcFamily", "IntelBDW",
448+
" Intel Broadwell Processor", [
449+
ProcIntelHSW,
453450
FeatureADX,
454451
FeatureRDSEED,
455-
FeatureSlowIncDec,
456-
FeatureLAHFSAHF
452+
FeatureSMAP
457453
]>;
454+
class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel,
455+
[ProcIntelBDW]>;
458456
def : BroadwellProc<"broadwell">;
459457

458+
def ProcIntelSKL : SubtargetFeature<"skl", "X86ProcFamily", "IntelSKL",
459+
" Intel Skylake Client Processor", [
460+
ProcIntelBDW,
461+
FeatureMPX,
462+
FeatureXSAVEC,
463+
FeatureXSAVES,
464+
FeatureSGX,
465+
FeatureCLFLUSHOPT
466+
]>;
467+
468+
// FIXME: define SKL model
469+
class SkylakeClientProc<string Name> : ProcessorModel<Name, HaswellModel,
470+
[ProcIntelSKL]>;
471+
def : SkylakeClientProc<"skl">;
472+
460473
// FIXME: define KNL model
461-
class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
462-
FeatureMMX,
474+
class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,[
475+
ProcIntelIVB,
463476
FeatureAVX512,
464-
FeatureFXSR,
465477
FeatureERI,
466478
FeatureCDI,
467479
FeaturePFI,
468-
FeatureCMPXCHG16B,
469-
FeaturePOPCNT,
470-
FeatureAES,
471-
FeaturePCLMUL,
472-
FeatureXSAVE,
473-
FeatureXSAVEOPT,
474-
FeatureRDRAND,
475-
FeatureF16C,
476-
FeatureFSGSBase,
480+
FeaturePREFETCHWT1,
481+
FeatureADX,
482+
FeatureRDSEED,
477483
FeatureMOVBE,
478484
FeatureLZCNT,
479485
FeatureBMI,
480486
FeatureBMI2,
481-
FeatureFMA,
482-
FeatureRTM,
483-
FeatureHLE,
484-
FeatureSlowIncDec,
485-
FeatureMPX,
486-
FeatureLAHFSAHF
487+
FeatureFMA
487488
]>;
488489
def : KnightsLandingProc<"knl">;
489490

490-
// FIXME: define SKX model
491-
class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
492-
FeatureMMX,
491+
def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", "IntelSKX",
492+
" Intel Skylake Server Processor", [
493+
ProcIntelSKL,
493494
FeatureAVX512,
494-
FeatureFXSR,
495495
FeatureCDI,
496496
FeatureDQI,
497497
FeatureBWI,
498498
FeatureVLX,
499499
FeaturePKU,
500-
FeatureCMPXCHG16B,
501-
FeatureSlowBTMem,
502-
FeaturePOPCNT,
503-
FeatureAES,
504-
FeaturePCLMUL,
505-
FeatureXSAVE,
506-
FeatureXSAVEOPT,
507-
FeatureRDRAND,
508-
FeatureF16C,
509-
FeatureFSGSBase,
510-
FeatureMOVBE,
511-
FeatureLZCNT,
512-
FeatureBMI,
513-
FeatureBMI2,
514-
FeatureFMA,
515-
FeatureRTM,
516-
FeatureHLE,
517-
FeatureADX,
518-
FeatureRDSEED,
519-
FeatureSlowIncDec,
520-
FeatureMPX,
521-
FeatureXSAVEC,
522-
FeatureXSAVES,
523-
FeatureLAHFSAHF
500+
FeaturePCOMMIT,
501+
FeatureCLWB
524502
]>;
525-
def : SkylakeProc<"skylake">;
526-
def : SkylakeProc<"skx">; // Legacy alias.
527503

528-
class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
529-
FeatureMMX,
530-
FeatureAVX512,
531-
FeatureFXSR,
532-
FeatureCDI,
533-
FeatureDQI,
534-
FeatureBWI,
535-
FeatureVLX,
536-
FeaturePKU,
537-
FeatureCMPXCHG16B,
538-
FeatureSlowBTMem,
539-
FeaturePOPCNT,
540-
FeatureAES,
541-
FeaturePCLMUL,
542-
FeatureXSAVE,
543-
FeatureXSAVEOPT,
544-
FeatureRDRAND,
545-
FeatureF16C,
546-
FeatureFSGSBase,
547-
FeatureMOVBE,
548-
FeatureLZCNT,
549-
FeatureBMI,
550-
FeatureBMI2,
504+
// FIXME: define SKX model
505+
class SkylakeServerProc<string Name> : ProcessorModel<Name, HaswellModel,
506+
[ ProcIntelSKX]>;
507+
def : SkylakeServerProc<"skylake">;
508+
def : SkylakeServerProc<"skx">; // Legacy alias.
509+
510+
def ProcIntelCNL : SubtargetFeature<"cnl", "X86ProcFamily", "IntelCNL",
511+
" Intel Cannonlake Processor", [
512+
ProcIntelSKX,
551513
FeatureVBMI,
552-
FeatureFMA,
553-
FeatureRTM,
554-
FeatureHLE,
555-
FeatureADX,
556-
FeatureRDSEED,
557-
FeatureSlowIncDec,
558-
FeatureMPX,
559-
FeatureXSAVEC,
560-
FeatureXSAVES,
561-
FeatureLAHFSAHF
514+
FeatureIFMA,
515+
FeatureSHA
562516
]>;
517+
518+
class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel,
519+
[ ProcIntelCNL ]>;
563520
def : CannonlakeProc<"cannonlake">;
564521
def : CannonlakeProc<"cnl">;
565522

‎llvm/lib/Target/X86/X86InstrInfo.td

+2
Original file line numberDiff line numberDiff line change
@@ -797,6 +797,8 @@ def HasBMI : Predicate<"Subtarget->hasBMI()">;
797797
def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
798798
def HasVBMI : Predicate<"Subtarget->hasVBMI()">,
799799
AssemblerPredicate<"FeatureVBMI", "AVX-512 VBMI ISA">;
800+
def HasIFMA : Predicate<"Subtarget->hasIFMA()">,
801+
AssemblerPredicate<"FeatureIFMA", "AVX-512 IFMA ISA">;
800802
def HasRTM : Predicate<"Subtarget->hasRTM()">;
801803
def HasHLE : Predicate<"Subtarget->hasHLE()">;
802804
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;

‎llvm/lib/Target/X86/X86Subtarget.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,7 @@ void X86Subtarget::initializeEnvironment() {
262262
HasBMI = false;
263263
HasBMI2 = false;
264264
HasVBMI = false;
265+
HasIFMA = false;
265266
HasRTM = false;
266267
HasHLE = false;
267268
HasERI = false;

‎llvm/lib/Target/X86/X86Subtarget.h

+31-2
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@ class X86Subtarget final : public X86GenSubtargetInfo {
5555
};
5656

5757
enum X86ProcFamilyEnum {
58-
Others, IntelAtom, IntelSLM
58+
Others, IntelAtom, IntelSLM, IntelSNB, IntelIVB, IntelHSW, IntelBDW,
59+
IntelKNL, IntelSKL, IntelSKX, IntelCNL
5960
};
6061

6162
/// X86 processor family: Intel Atom, and others
@@ -137,6 +138,9 @@ class X86Subtarget final : public X86GenSubtargetInfo {
137138
/// Processor has VBMI instructions.
138139
bool HasVBMI;
139140

141+
/// Processor has Integer Fused Multiply Add
142+
bool HasIFMA;
143+
140144
/// Processor has RTM instructions.
141145
bool HasRTM;
142146

@@ -158,6 +162,9 @@ class X86Subtarget final : public X86GenSubtargetInfo {
158162
/// Processor has LAHF/SAHF instructions.
159163
bool HasLAHFSAHF;
160164

165+
/// Processor has Prefetch with intent to Write instruction
166+
bool HasPFPREFETCHWT1;
167+
161168
/// True if BT (bit test) of memory instructions are slow.
162169
bool IsBTMemSlow;
163170

@@ -229,9 +236,30 @@ class X86Subtarget final : public X86GenSubtargetInfo {
229236
/// Processor has PKU extenstions
230237
bool HasPKU;
231238

232-
/// Processot supports MPX - Memory Protection Extensions
239+
/// Processor supports MPX - Memory Protection Extensions
233240
bool HasMPX;
234241

242+
/// Processor supports Invalidate Process-Context Identifier
243+
bool HasInvPCId;
244+
245+
/// Processor has VM Functions
246+
bool HasVMFUNC;
247+
248+
/// Processor has Supervisor Mode Access Protection
249+
bool HasSMAP;
250+
251+
/// Processor has Software Guard Extensions
252+
bool HasSGX;
253+
254+
/// Processor supports Flush Cache Line instruction
255+
bool HasCLFLUSHOPT;
256+
257+
/// Processor has Persistent Commit feature
258+
bool HasPCOMMIT;
259+
260+
/// Processor supports Cache Line Write Back instruction
261+
bool HasCLWB;
262+
235263
/// Use software floating point for code generation.
236264
bool UseSoftFloat;
237265

@@ -378,6 +406,7 @@ class X86Subtarget final : public X86GenSubtargetInfo {
378406
bool hasBMI() const { return HasBMI; }
379407
bool hasBMI2() const { return HasBMI2; }
380408
bool hasVBMI() const { return HasVBMI; }
409+
bool hasIFMA() const { return HasIFMA; }
381410
bool hasRTM() const { return HasRTM; }
382411
bool hasHLE() const { return HasHLE; }
383412
bool hasADX() const { return HasADX; }

‎llvm/test/CodeGen/X86/avx512bw-intrinsics.ll

+196-56
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