@@ -125,6 +125,9 @@ def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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+ def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
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+ "true",
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+ "Prefetch with Intent to Write and T1 Hint">;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
@@ -137,6 +140,9 @@ def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
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"Enable AVX-512 Vector Bit Manipulation Instructions",
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[FeatureAVX512]>;
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+ def FeatureIFMA : SubtargetFeature<"ifma", "HasIFMA", "true",
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+ "Enable AVX-512 Integer Fused Multiple-Add",
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+ [FeatureAVX512]>;
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def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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"Enable protection keys">;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
@@ -202,6 +208,20 @@ def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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+ def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
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+ "Invalidate Process-Context Identifier">;
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+ def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
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+ "VM Functions">;
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+ def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
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+ "Supervisor Mode Access Protection">;
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+ def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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+ "Enable Software Guard Extensions">;
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+ def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
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+ "Flush A Cache Line Optimized">;
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+ def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
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+ "Enable Persistent Commit">;
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+ def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
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+ "Cache Line Write Back">;
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// TODO: This feature ought to be renamed.
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// What it really refers to are CPUs for which certain instructions
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// (which ones besides the example below?) are microcoded.
@@ -365,201 +385,138 @@ def : WestmereProc<"westmere">;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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- class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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+ def ProcIntelSNB : SubtargetFeature<"snb", "X86ProcFamily", "IntelSNB",
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+ " Intel SandyBridge Processor", [
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FeatureMMX,
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FeatureAVX,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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FeatureLAHFSAHF
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]>;
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+
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+ class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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+ ProcIntelSNB,
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+ FeatureSlowBTMem,
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+ FeatureSlowUAMem32
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+ ]>;
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def : SandyBridgeProc<"sandybridge">;
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def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
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- class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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- FeatureMMX,
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- FeatureAVX,
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- FeatureFXSR,
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- FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeatureSlowUAMem32,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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+ def ProcIntelIVB : SubtargetFeature<"ivb", "X86ProcFamily", "IntelIVB",
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+ " Intel IvyBridge Processor", [
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+ ProcIntelSNB,
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FeatureRDRAND,
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FeatureF16C,
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- FeatureFSGSBase,
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- FeatureLAHFSAHF
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+ FeatureFSGSBase
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+ ]>;
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+
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+ class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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+ ProcIntelIVB,
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+ FeatureSlowBTMem,
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+ FeatureSlowUAMem32
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]>;
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def : IvyBridgeProc<"ivybridge">;
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def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
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- class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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- FeatureMMX,
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+ def ProcIntelHSW : SubtargetFeature<"hsw", "X86ProcFamily", "IntelHSW",
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+ " Intel Haswell Processor", [
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+ ProcIntelIVB,
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FeatureAVX2,
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- FeatureFXSR,
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- FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureRDRAND,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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- FeatureF16C,
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- FeatureFSGSBase,
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- FeatureMOVBE,
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- FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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+ FeatureLZCNT,
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+ FeatureMOVBE,
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+ FeatureINVPCID,
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+ FeatureVMFUNC,
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FeatureRTM,
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FeatureHLE,
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- FeatureSlowIncDec,
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- FeatureLAHFSAHF
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+ FeatureSlowIncDec
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]>;
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+
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+ class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel,
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+ [ProcIntelHSW]>;
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def : HaswellProc<"haswell">;
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def : HaswellProc<"core-avx2">; // Legacy alias.
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- class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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- FeatureMMX,
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- FeatureAVX2,
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- FeatureFXSR,
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- FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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- FeatureRDRAND,
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- FeatureF16C,
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- FeatureFSGSBase,
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- FeatureMOVBE,
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- FeatureLZCNT,
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- FeatureBMI,
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- FeatureBMI2,
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- FeatureFMA,
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- FeatureRTM,
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- FeatureHLE,
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+ def ProcIntelBDW : SubtargetFeature<"bdw", "X86ProcFamily", "IntelBDW",
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+ " Intel Broadwell Processor", [
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+ ProcIntelHSW,
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FeatureADX,
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FeatureRDSEED,
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- FeatureSlowIncDec,
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- FeatureLAHFSAHF
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+ FeatureSMAP
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]>;
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+ class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel,
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+ [ProcIntelBDW]>;
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def : BroadwellProc<"broadwell">;
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+ def ProcIntelSKL : SubtargetFeature<"skl", "X86ProcFamily", "IntelSKL",
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+ " Intel Skylake Client Processor", [
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+ ProcIntelBDW,
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+ FeatureMPX,
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+ FeatureXSAVEC,
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+ FeatureXSAVES,
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+ FeatureSGX,
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+ FeatureCLFLUSHOPT
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+ ]>;
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+
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+ // FIXME: define SKL model
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+ class SkylakeClientProc<string Name> : ProcessorModel<Name, HaswellModel,
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+ [ProcIntelSKL]>;
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+ def : SkylakeClientProc<"skl">;
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+
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// FIXME: define KNL model
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- class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
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- FeatureMMX ,
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+ class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,[
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+ ProcIntelIVB ,
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FeatureAVX512,
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- FeatureFXSR,
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FeatureERI,
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FeatureCDI,
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FeaturePFI,
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- FeatureCMPXCHG16B,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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- FeatureRDRAND,
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- FeatureF16C,
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- FeatureFSGSBase,
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+ FeaturePREFETCHWT1,
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+ FeatureADX,
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+ FeatureRDSEED,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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- FeatureFMA,
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- FeatureRTM,
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- FeatureHLE,
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- FeatureSlowIncDec,
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- FeatureMPX,
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- FeatureLAHFSAHF
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+ FeatureFMA
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]>;
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def : KnightsLandingProc<"knl">;
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- // FIXME: define SKX model
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- class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel , [
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- FeatureMMX ,
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+ def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", "IntelSKX",
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+ " Intel Skylake Server Processor" , [
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+ ProcIntelSKL ,
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FeatureAVX512,
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- FeatureFXSR,
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FeatureCDI,
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FeatureDQI,
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FeatureBWI,
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FeatureVLX,
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FeaturePKU,
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- FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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- FeatureRDRAND,
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- FeatureF16C,
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- FeatureFSGSBase,
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- FeatureMOVBE,
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- FeatureLZCNT,
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- FeatureBMI,
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- FeatureBMI2,
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- FeatureFMA,
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- FeatureRTM,
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- FeatureHLE,
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- FeatureADX,
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- FeatureRDSEED,
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- FeatureSlowIncDec,
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- FeatureMPX,
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- FeatureXSAVEC,
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- FeatureXSAVES,
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- FeatureLAHFSAHF
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+ FeaturePCOMMIT,
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+ FeatureCLWB
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]>;
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- def : SkylakeProc<"skylake">;
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- def : SkylakeProc<"skx">; // Legacy alias.
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- class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
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- FeatureMMX,
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- FeatureAVX512,
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- FeatureFXSR,
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- FeatureCDI,
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- FeatureDQI,
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- FeatureBWI,
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- FeatureVLX,
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- FeaturePKU,
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- FeatureCMPXCHG16B,
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- FeatureSlowBTMem,
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- FeaturePOPCNT,
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- FeatureAES,
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- FeaturePCLMUL,
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- FeatureXSAVE,
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- FeatureXSAVEOPT,
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- FeatureRDRAND,
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- FeatureF16C,
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- FeatureFSGSBase,
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- FeatureMOVBE,
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- FeatureLZCNT,
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- FeatureBMI,
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- FeatureBMI2,
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+ // FIXME: define SKX model
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+ class SkylakeServerProc<string Name> : ProcessorModel<Name, HaswellModel,
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+ [ ProcIntelSKX]>;
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+ def : SkylakeServerProc<"skylake">;
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+ def : SkylakeServerProc<"skx">; // Legacy alias.
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+
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+ def ProcIntelCNL : SubtargetFeature<"cnl", "X86ProcFamily", "IntelCNL",
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+ " Intel Cannonlake Processor", [
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+ ProcIntelSKX,
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FeatureVBMI,
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- FeatureFMA,
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- FeatureRTM,
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- FeatureHLE,
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- FeatureADX,
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- FeatureRDSEED,
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- FeatureSlowIncDec,
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- FeatureMPX,
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- FeatureXSAVEC,
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- FeatureXSAVES,
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- FeatureLAHFSAHF
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+ FeatureIFMA,
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+ FeatureSHA
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]>;
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+
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+ class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel,
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+ [ ProcIntelCNL ]>;
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def : CannonlakeProc<"cannonlake">;
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def : CannonlakeProc<"cnl">;
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