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dsandersllvmdsandersllvm
committedJul 14, 2015
[mips] Fix li/la differences between IAS and GAS.
Summary: - Signed 16-bit should have priority over unsigned. - For la, unsigned 16-bit must use ori+addu rather than directly use ori. - Correct tests on 32-bit immediates with 64-bit predicates by sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000) should be true and use addiu. Also split li/la testing into separate files due to their size. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10967 llvm-svn: 242139
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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+83-82
Original file line numberDiff line numberDiff line change
@@ -1727,37 +1727,59 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
17271727
}
17281728

17291729
namespace {
1730+
void emitRX(unsigned Opcode, unsigned DstReg, MCOperand Imm, SMLoc IDLoc,
1731+
SmallVectorImpl<MCInst> &Instructions) {
1732+
MCInst tmpInst;
1733+
tmpInst.setOpcode(Opcode);
1734+
tmpInst.addOperand(MCOperand::createReg(DstReg));
1735+
tmpInst.addOperand(Imm);
1736+
tmpInst.setLoc(IDLoc);
1737+
Instructions.push_back(tmpInst);
1738+
}
1739+
1740+
void emitRI(unsigned Opcode, unsigned DstReg, int16_t Imm, SMLoc IDLoc,
1741+
SmallVectorImpl<MCInst> &Instructions) {
1742+
emitRX(Opcode, DstReg, MCOperand::createImm(Imm), IDLoc, Instructions);
1743+
}
1744+
1745+
1746+
void emitRRX(unsigned Opcode, unsigned DstReg, unsigned SrcReg, MCOperand Imm,
1747+
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
1748+
MCInst tmpInst;
1749+
tmpInst.setOpcode(Opcode);
1750+
tmpInst.addOperand(MCOperand::createReg(DstReg));
1751+
tmpInst.addOperand(MCOperand::createReg(SrcReg));
1752+
tmpInst.addOperand(Imm);
1753+
tmpInst.setLoc(IDLoc);
1754+
Instructions.push_back(tmpInst);
1755+
}
1756+
1757+
void emitRRR(unsigned Opcode, unsigned DstReg, unsigned SrcReg,
1758+
unsigned SrcReg2, SMLoc IDLoc,
1759+
SmallVectorImpl<MCInst> &Instructions) {
1760+
emitRRX(Opcode, DstReg, SrcReg, MCOperand::createReg(SrcReg2), IDLoc,
1761+
Instructions);
1762+
}
1763+
1764+
void emitRRI(unsigned Opcode, unsigned DstReg, unsigned SrcReg, int16_t Imm,
1765+
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
1766+
emitRRX(Opcode, DstReg, SrcReg, MCOperand::createImm(Imm), IDLoc,
1767+
Instructions);
1768+
}
1769+
17301770
template <unsigned ShiftAmount>
17311771
void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
17321772
SmallVectorImpl<MCInst> &Instructions) {
1733-
MCInst tmpInst;
1734-
if (ShiftAmount >= 32) {
1735-
tmpInst.setOpcode(Mips::DSLL32);
1736-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1737-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1738-
tmpInst.addOperand(MCOperand::createImm(ShiftAmount - 32));
1739-
tmpInst.setLoc(IDLoc);
1740-
Instructions.push_back(tmpInst);
1741-
tmpInst.clear();
1742-
} else if (ShiftAmount > 0) {
1743-
tmpInst.setOpcode(Mips::DSLL);
1744-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1745-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1746-
tmpInst.addOperand(MCOperand::createImm(ShiftAmount));
1747-
tmpInst.setLoc(IDLoc);
1748-
Instructions.push_back(tmpInst);
1749-
tmpInst.clear();
1750-
}
1773+
if (ShiftAmount >= 32)
1774+
emitRRI(Mips::DSLL32, RegNo, RegNo, ShiftAmount - 32, IDLoc, Instructions);
1775+
else if (ShiftAmount > 0)
1776+
emitRRI(Mips::DSLL, RegNo, RegNo, ShiftAmount, IDLoc, Instructions);
1777+
17511778
// There's no need for an ORi if the immediate is 0.
17521779
if (Operand.isImm() && Operand.getImm() == 0)
17531780
return;
17541781

1755-
tmpInst.setOpcode(Mips::ORi);
1756-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1757-
tmpInst.addOperand(MCOperand::createReg(RegNo));
1758-
tmpInst.addOperand(Operand);
1759-
tmpInst.setLoc(IDLoc);
1760-
Instructions.push_back(tmpInst);
1782+
emitRRX(Mips::ORi, RegNo, RegNo, Operand, IDLoc, Instructions);
17611783
}
17621784

17631785
template <unsigned ShiftAmount>
@@ -1818,12 +1840,22 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
18181840
return true;
18191841
}
18201842

1843+
if (Is32BitImm) {
1844+
if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
1845+
// Sign extend up to 64-bit so that the predicates match the hardware
1846+
// behaviour. In particular, isInt<16>(0xffff8000) and similar should be
1847+
// true.
1848+
ImmValue = SignExtend64<32>(ImmValue);
1849+
} else {
1850+
Error(IDLoc, "instruction requires a 32-bit immediate");
1851+
return true;
1852+
}
1853+
}
1854+
18211855
bool UseSrcReg = false;
18221856
if (SrcReg != Mips::NoRegister)
18231857
UseSrcReg = true;
18241858

1825-
MCInst tmpInst;
1826-
18271859
unsigned TmpReg = DstReg;
18281860
if (UseSrcReg && (DstReg == SrcReg)) {
18291861
// At this point we need AT to perform the expansions and we exit if it is
@@ -1834,29 +1866,26 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
18341866
TmpReg = ATReg;
18351867
}
18361868

1837-
tmpInst.setLoc(IDLoc);
18381869
// FIXME: gas has a special case for values that are 000...1111, which
18391870
// becomes a li -1 and then a dsrl
1840-
if (0 <= ImmValue && ImmValue <= 65535) {
1841-
// For unsigned and positive signed 16-bit values (0 <= j <= 65535):
1842-
// li d,j => ori d,$zero,j
1843-
if (!UseSrcReg)
1844-
SrcReg = isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
1845-
tmpInst.setOpcode(Mips::ORi);
1846-
tmpInst.addOperand(MCOperand::createReg(DstReg));
1847-
tmpInst.addOperand(MCOperand::createReg(SrcReg));
1848-
tmpInst.addOperand(MCOperand::createImm(ImmValue));
1849-
Instructions.push_back(tmpInst);
1850-
} else if (ImmValue < 0 && ImmValue >= -32768) {
1851-
// For negative signed 16-bit values (-32768 <= j < 0):
1871+
if (isInt<16>(ImmValue)) {
18521872
// li d,j => addiu d,$zero,j
18531873
if (!UseSrcReg)
18541874
SrcReg = Mips::ZERO;
1855-
tmpInst.setOpcode(Mips::ADDiu);
1856-
tmpInst.addOperand(MCOperand::createReg(DstReg));
1857-
tmpInst.addOperand(MCOperand::createReg(SrcReg));
1858-
tmpInst.addOperand(MCOperand::createImm(ImmValue));
1859-
Instructions.push_back(tmpInst);
1875+
emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, Instructions);
1876+
} else if (isUInt<16>(ImmValue)) {
1877+
// li d,j => ori d,$zero,j
1878+
unsigned TmpReg = DstReg;
1879+
if (SrcReg == DstReg) {
1880+
unsigned ATReg = getATReg(IDLoc);
1881+
if (!ATReg)
1882+
return true;
1883+
TmpReg = ATReg;
1884+
}
1885+
1886+
emitRRI(Mips::ORi, TmpReg, Mips::ZERO, ImmValue, IDLoc, Instructions);
1887+
if (UseSrcReg)
1888+
emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Instructions);
18601889
} else if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
18611890
warnIfNoMacro(IDLoc);
18621891

@@ -1869,30 +1898,16 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
18691898
if (!Is32BitImm && !isInt<32>(ImmValue)) {
18701899
// For DLI, expand to an ORi instead of a LUi to avoid sign-extending the
18711900
// upper 32 bits.
1872-
tmpInst.setOpcode(Mips::ORi);
1873-
tmpInst.addOperand(MCOperand::createReg(TmpReg));
1874-
tmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
1875-
tmpInst.addOperand(MCOperand::createImm(Bits31To16));
1876-
tmpInst.setLoc(IDLoc);
1877-
Instructions.push_back(tmpInst);
1878-
// Move the value to the upper 16 bits by doing a 16-bit left shift.
1879-
createLShiftOri<16>(0, TmpReg, IDLoc, Instructions);
1880-
} else {
1881-
tmpInst.setOpcode(Mips::LUi);
1882-
tmpInst.addOperand(MCOperand::createReg(TmpReg));
1883-
tmpInst.addOperand(MCOperand::createImm(Bits31To16));
1884-
Instructions.push_back(tmpInst);
1885-
}
1901+
emitRRI(Mips::ORi, TmpReg, Mips::ZERO, Bits31To16, IDLoc, Instructions);
1902+
emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, Instructions);
1903+
} else
1904+
emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, Instructions);
18861905
createLShiftOri<0>(Bits15To0, TmpReg, IDLoc, Instructions);
18871906

18881907
if (UseSrcReg)
18891908
createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
18901909

18911910
} else if ((ImmValue & (0xffffLL << 48)) == 0) {
1892-
if (Is32BitImm) {
1893-
Error(IDLoc, "instruction requires a 32-bit immediate");
1894-
return true;
1895-
}
18961911
warnIfNoMacro(IDLoc);
18971912

18981913
// <------- lo32 ------>
@@ -1912,21 +1927,14 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
19121927
uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
19131928
uint16_t Bits15To0 = ImmValue & 0xffff;
19141929

1915-
tmpInst.setOpcode(Mips::LUi);
1916-
tmpInst.addOperand(MCOperand::createReg(TmpReg));
1917-
tmpInst.addOperand(MCOperand::createImm(Bits47To32));
1918-
Instructions.push_back(tmpInst);
1930+
emitRI(Mips::LUi, TmpReg, Bits47To32, IDLoc, Instructions);
19191931
createLShiftOri<0>(Bits31To16, TmpReg, IDLoc, Instructions);
19201932
createLShiftOri<16>(Bits15To0, TmpReg, IDLoc, Instructions);
19211933

19221934
if (UseSrcReg)
19231935
createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
19241936

19251937
} else {
1926-
if (Is32BitImm) {
1927-
Error(IDLoc, "instruction requires a 32-bit immediate");
1928-
return true;
1929-
}
19301938
warnIfNoMacro(IDLoc);
19311939

19321940
// <------- hi32 ------> <------- lo32 ------>
@@ -1948,10 +1956,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
19481956
uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
19491957
uint16_t Bits15To0 = ImmValue & 0xffff;
19501958

1951-
tmpInst.setOpcode(Mips::LUi);
1952-
tmpInst.addOperand(MCOperand::createReg(TmpReg));
1953-
tmpInst.addOperand(MCOperand::createImm(Bits63To48));
1954-
Instructions.push_back(tmpInst);
1959+
emitRI(Mips::LUi, TmpReg, Bits63To48, IDLoc, Instructions);
19551960
createLShiftOri<0>(Bits47To32, TmpReg, IDLoc, Instructions);
19561961

19571962
// When Bits31To16 is 0, do a left shift of 32 bits instead of doing
@@ -2096,8 +2101,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(
20962101
tmpInst.addOperand(MCOperand::createExpr(HiExpr));
20972102
Instructions.push_back(tmpInst);
20982103

2099-
createLShiftOri<0>(MCOperand::createExpr(LoExpr), TmpReg, SMLoc(),
2100-
Instructions);
2104+
emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), SMLoc(),
2105+
Instructions);
21012106
}
21022107

21032108
if (UseSrcReg)
@@ -2708,12 +2713,8 @@ void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
27082713
void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
27092714
unsigned TrgReg, bool Is64Bit,
27102715
SmallVectorImpl<MCInst> &Instructions) {
2711-
MCInst AdduInst;
2712-
AdduInst.setOpcode(Is64Bit ? Mips::DADDu : Mips::ADDu);
2713-
AdduInst.addOperand(MCOperand::createReg(DstReg));
2714-
AdduInst.addOperand(MCOperand::createReg(SrcReg));
2715-
AdduInst.addOperand(MCOperand::createReg(TrgReg));
2716-
Instructions.push_back(AdduInst);
2716+
emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
2717+
Instructions);
27172718
}
27182719

27192720
unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {

‎llvm/test/MC/Mips/macro-la-bad.s

+17
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
2+
# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
3+
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
4+
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N32-ONLY
5+
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
6+
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
7+
8+
.text
9+
la $5, 0x100000000
10+
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
11+
# 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
12+
la $5, 0x100000000($6)
13+
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14+
# 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
15+
la $5, symbol
16+
# N64-ONLY: :[[@LINE-1]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol
17+
# N32-ONLY-NOT: :[[@LINE-2]]:3: warning: instruction loads the 32-bit address of a 64-bit symbol

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