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Commit 0b3e978

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author
Toma Tabacu
committedJun 23, 2015
[mips] [IAS] Add support for generating DADDu to createAddu(). NFC.
Summary: This isn't used right now, but it will be in some upcoming changes. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10568 llvm-svn: 240407
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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+7-7
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ class MipsAsmParser : public MCTargetAsmParser {
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SmallVectorImpl<MCInst> &Instructions);
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void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
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SmallVectorImpl<MCInst> &Instructions);
221+
bool Is64Bit, SmallVectorImpl<MCInst> &Instructions);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@@ -1836,7 +1836,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
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createLShiftOri<0>(Bits15To0, TmpReg, IDLoc, Instructions);
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if (UseSrcReg)
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createAddu(DstReg, TmpReg, SrcReg, Instructions);
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createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
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} else if ((ImmValue & (0xffffLL << 48)) == 0) {
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if (Is32BitImm) {
@@ -1870,7 +1870,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
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createLShiftOri<16>(Bits15To0, TmpReg, IDLoc, Instructions);
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if (UseSrcReg)
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createAddu(DstReg, TmpReg, SrcReg, Instructions);
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createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
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} else {
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if (Is32BitImm) {
@@ -1914,7 +1914,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
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}
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if (UseSrcReg)
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createAddu(DstReg, TmpReg, SrcReg, Instructions);
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createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
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}
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return false;
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}
@@ -2051,7 +2051,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(
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}
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if (UseSrcReg)
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createAddu(DstReg, TmpReg, SrcReg, Instructions);
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createAddu(DstReg, TmpReg, SrcReg, !Is32BitSym, Instructions);
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return false;
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}
@@ -2488,10 +2488,10 @@ void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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}
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void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
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unsigned TrgReg,
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unsigned TrgReg, bool Is64Bit,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst AdduInst;
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AdduInst.setOpcode(Mips::ADDu);
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AdduInst.setOpcode(Is64Bit ? Mips::DADDu : Mips::ADDu);
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AdduInst.addOperand(MCOperand::createReg(DstReg));
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AdduInst.addOperand(MCOperand::createReg(SrcReg));
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AdduInst.addOperand(MCOperand::createReg(TrgReg));

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