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atanasyanatanasyan
committedMay 7, 2015
[MIPS] Move MIPS ABI flags structure constants to the separate header
http://reviews.llvm.org/D9517 The separate header file allows to reuse the MIPS ABI flags structure constants in other LLVM tools like the llvm-readobj. No functional changes. llvm-svn: 236732
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llvmorg-21-initllvmorg-3.7.0-rc1
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‎llvm/include/llvm/Support/MipsABIFlags.h

+102
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
//===--- MipsABIFlags.h - MIPS ABI flags ----------------------------------===//
2+
//
3+
// The LLVM Compiler Infrastructure
4+
//
5+
// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
7+
//
8+
//===----------------------------------------------------------------------===//
9+
//
10+
// This file defines the constants for the ABI flags structure contained
11+
// in the .MIPS.abiflags section.
12+
//
13+
// https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
14+
//
15+
//===----------------------------------------------------------------------===//
16+
17+
#ifndef LLVM_SUPPORT_MIPSABIFLAGS_H
18+
#define LLVM_SUPPORT_MIPSABIFLAGS_H
19+
20+
namespace llvm {
21+
namespace Mips {
22+
23+
// Values for the xxx_size bytes of an ABI flags structure.
24+
enum AFL_REG {
25+
AFL_REG_NONE = 0x00, // No registers
26+
AFL_REG_32 = 0x01, // 32-bit registers
27+
AFL_REG_64 = 0x02, // 64-bit registers
28+
AFL_REG_128 = 0x03 // 128-bit registers
29+
};
30+
31+
// Masks for the ases word of an ABI flags structure.
32+
enum AFL_ASE {
33+
AFL_ASE_DSP = 0x00000001, // DSP ASE
34+
AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE
35+
AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme
36+
AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE
37+
AFL_ASE_MDMX = 0x00000010, // MDMX ASE
38+
AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE
39+
AFL_ASE_MT = 0x00000040, // MT ASE
40+
AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE
41+
AFL_ASE_VIRT = 0x00000100, // VZ ASE
42+
AFL_ASE_MSA = 0x00000200, // MSA ASE
43+
AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE
44+
AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
45+
AFL_ASE_XPA = 0x00001000 // XPA ASE
46+
};
47+
48+
// Values for the isa_ext word of an ABI flags structure.
49+
enum AFL_EXT {
50+
AFL_EXT_NONE = 0, // None
51+
AFL_EXT_XLR = 1, // RMI Xlr instruction
52+
AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2
53+
AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP
54+
AFL_EXT_LOONGSON_3A = 4, // Loongson 3A
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AFL_EXT_OCTEON = 5, // Cavium Networks Octeon
56+
AFL_EXT_5900 = 6, // MIPS R5900 instruction
57+
AFL_EXT_4650 = 7, // MIPS R4650 instruction
58+
AFL_EXT_4010 = 8, // LSI R4010 instruction
59+
AFL_EXT_4100 = 9, // NEC VR4100 instruction
60+
AFL_EXT_3900 = 10, // Toshiba R3900 instruction
61+
AFL_EXT_10000 = 11, // MIPS R10000 instruction
62+
AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction
63+
AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction
64+
AFL_EXT_4120 = 14, // NEC VR4120 instruction
65+
AFL_EXT_5400 = 15, // NEC VR5400 instruction
66+
AFL_EXT_5500 = 16, // NEC VR5500 instruction
67+
AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E
68+
AFL_EXT_LOONGSON_2F = 18, // ST Microelectronics Loongson 2F
69+
AFL_EXT_OCTEON3 = 19 // Cavium Networks Octeon3
70+
};
71+
72+
// Values for the flags1 word of an ABI flags structure.
73+
enum AFL_FLAGS1 { AFL_FLAGS1_ODDSPREG = 1 };
74+
75+
// MIPS object attribute tags
76+
enum {
77+
Tag_GNU_MIPS_ABI_FP = 4, // Floating-point ABI used by this object file
78+
Tag_GNU_MIPS_ABI_MSA = 8, // MSA ABI used by this object file
79+
};
80+
81+
// Values for the fp_abi word of an ABI flags structure
82+
// and for the Tag_GNU_MIPS_ABI_FP attribute tag.
83+
enum Val_GNU_MIPS_ABI_FP {
84+
Val_GNU_MIPS_ABI_FP_ANY = 0, // not tagged
85+
Val_GNU_MIPS_ABI_FP_DOUBLE = 1, // hard float / -mdouble-float
86+
Val_GNU_MIPS_ABI_FP_SINGLE = 2, // hard float / -msingle-float
87+
Val_GNU_MIPS_ABI_FP_SOFT = 3, // soft float
88+
Val_GNU_MIPS_ABI_FP_OLD_64 = 4, // -mips32r2 -mfp64
89+
Val_GNU_MIPS_ABI_FP_XX = 5, // -mfpxx
90+
Val_GNU_MIPS_ABI_FP_64 = 6, // -mips32r2 -mfp64
91+
Val_GNU_MIPS_ABI_FP_64A = 7 // -mips32r2 -mfp64 -mno-odd-spreg
92+
};
93+
94+
// Values for the Tag_GNU_MIPS_ABI_MSA attribute tag.
95+
enum Val_GNU_MIPS_ABI_MSA {
96+
Val_GNU_MIPS_ABI_MSA_ANY = 0, // not tagged
97+
Val_GNU_MIPS_ABI_MSA_128 = 1 // 128-bit MSA
98+
};
99+
}
100+
}
101+
102+
#endif

‎llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp

+8-7
Original file line numberDiff line numberDiff line change
@@ -14,17 +14,18 @@ using namespace llvm;
1414
uint8_t MipsABIFlagsSection::getFpABIValue() {
1515
switch (FpABI) {
1616
case FpABIKind::ANY:
17-
return Val_GNU_MIPS_ABI_FP_ANY;
17+
return Mips::Val_GNU_MIPS_ABI_FP_ANY;
1818
case FpABIKind::SOFT:
19-
return Val_GNU_MIPS_ABI_FP_SOFT;
19+
return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
2020
case FpABIKind::XX:
21-
return Val_GNU_MIPS_ABI_FP_XX;
21+
return Mips::Val_GNU_MIPS_ABI_FP_XX;
2222
case FpABIKind::S32:
23-
return Val_GNU_MIPS_ABI_FP_DOUBLE;
23+
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
2424
case FpABIKind::S64:
2525
if (Is32BitABI)
26-
return OddSPReg ? Val_GNU_MIPS_ABI_FP_64 : Val_GNU_MIPS_ABI_FP_64A;
27-
return Val_GNU_MIPS_ABI_FP_DOUBLE;
26+
return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
27+
: Mips::Val_GNU_MIPS_ABI_FP_64A;
28+
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
2829
}
2930

3031
llvm_unreachable("unexpected fp abi value");
@@ -45,7 +46,7 @@ StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) {
4546

4647
uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
4748
if (FpABI == FpABIKind::XX)
48-
return (uint8_t)AFL_REG_32;
49+
return (uint8_t)Mips::AFL_REG_32;
4950
return (uint8_t)CPR1Size;
5051
}
5152

‎llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h

+18-77
Original file line numberDiff line numberDiff line change
@@ -11,73 +11,13 @@
1111
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
1212

1313
#include "llvm/MC/MCStreamer.h"
14+
#include "llvm/Support/MipsABIFlags.h"
1415

1516
namespace llvm {
1617

1718
class MCStreamer;
1819

1920
struct MipsABIFlagsSection {
20-
// Values for the xxx_size bytes of an ABI flags structure.
21-
enum AFL_REG {
22-
AFL_REG_NONE = 0x00, // No registers.
23-
AFL_REG_32 = 0x01, // 32-bit registers.
24-
AFL_REG_64 = 0x02, // 64-bit registers.
25-
AFL_REG_128 = 0x03 // 128-bit registers.
26-
};
27-
28-
// Masks for the ases word of an ABI flags structure.
29-
enum AFL_ASE {
30-
AFL_ASE_DSP = 0x00000001, // DSP ASE.
31-
AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE.
32-
AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme.
33-
AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE.
34-
AFL_ASE_MDMX = 0x00000010, // MDMX ASE.
35-
AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE.
36-
AFL_ASE_MT = 0x00000040, // MT ASE.
37-
AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE.
38-
AFL_ASE_VIRT = 0x00000100, // VZ ASE.
39-
AFL_ASE_MSA = 0x00000200, // MSA ASE.
40-
AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE.
41-
AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE.
42-
AFL_ASE_XPA = 0x00001000 // XPA ASE.
43-
};
44-
45-
// Values for the isa_ext word of an ABI flags structure.
46-
enum AFL_EXT {
47-
AFL_EXT_XLR = 1, // RMI Xlr instruction.
48-
AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2.
49-
AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP.
50-
AFL_EXT_LOONGSON_3A = 4, // Loongson 3A.
51-
AFL_EXT_OCTEON = 5, // Cavium Networks Octeon.
52-
AFL_EXT_5900 = 6, // MIPS R5900 instruction.
53-
AFL_EXT_4650 = 7, // MIPS R4650 instruction.
54-
AFL_EXT_4010 = 8, // LSI R4010 instruction.
55-
AFL_EXT_4100 = 9, // NEC VR4100 instruction.
56-
AFL_EXT_3900 = 10, // Toshiba R3900 instruction.
57-
AFL_EXT_10000 = 11, // MIPS R10000 instruction.
58-
AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction.
59-
AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction.
60-
AFL_EXT_4120 = 14, // NEC VR4120 instruction.
61-
AFL_EXT_5400 = 15, // NEC VR5400 instruction.
62-
AFL_EXT_5500 = 16, // NEC VR5500 instruction.
63-
AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E.
64-
AFL_EXT_LOONGSON_2F = 18 // ST Microelectronics Loongson 2F.
65-
};
66-
67-
// Values for the fp_abi word of an ABI flags structure.
68-
enum Val_GNU_MIPS_ABI {
69-
Val_GNU_MIPS_ABI_FP_ANY = 0,
70-
Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
71-
Val_GNU_MIPS_ABI_FP_SOFT = 3,
72-
Val_GNU_MIPS_ABI_FP_XX = 5,
73-
Val_GNU_MIPS_ABI_FP_64 = 6,
74-
Val_GNU_MIPS_ABI_FP_64A = 7
75-
};
76-
77-
enum AFL_FLAGS1 {
78-
AFL_FLAGS1_ODDSPREG = 1
79-
};
80-
8121
// Internal representation of the fp_abi related values used in .module.
8222
enum class FpABIKind { ANY, XX, S32, S64, SOFT };
8323

@@ -88,11 +28,11 @@ struct MipsABIFlagsSection {
8828
// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
8929
uint8_t ISARevision;
9030
// The size of general purpose registers.
91-
AFL_REG GPRSize;
31+
Mips::AFL_REG GPRSize;
9232
// The size of co-processor 1 registers.
93-
AFL_REG CPR1Size;
33+
Mips::AFL_REG CPR1Size;
9434
// The size of co-processor 2 registers.
95-
AFL_REG CPR2Size;
35+
Mips::AFL_REG CPR2Size;
9636
// Processor-specific extension.
9737
uint32_t ISAExtensionSet;
9838
// Mask of ASEs used.
@@ -108,9 +48,10 @@ struct MipsABIFlagsSection {
10848

10949
public:
11050
MipsABIFlagsSection()
111-
: Version(0), ISALevel(0), ISARevision(0), GPRSize(AFL_REG_NONE),
112-
CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE), ISAExtensionSet(0),
113-
ASESet(0), OddSPReg(false), Is32BitABI(false), FpABI(FpABIKind::ANY) {}
51+
: Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
52+
CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
53+
ISAExtensionSet(0), ASESet(0), OddSPReg(false), Is32BitABI(false),
54+
FpABI(FpABIKind::ANY) {}
11455

11556
uint16_t getVersionValue() { return (uint16_t)Version; }
11657
uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
@@ -126,7 +67,7 @@ struct MipsABIFlagsSection {
12667
uint32_t Value = 0;
12768

12869
if (OddSPReg)
129-
Value |= (uint32_t)AFL_FLAGS1_ODDSPREG;
70+
Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
13071

13172
return Value;
13273
}
@@ -185,32 +126,32 @@ struct MipsABIFlagsSection {
185126

186127
template <class PredicateLibrary>
187128
void setGPRSizeFromPredicates(const PredicateLibrary &P) {
188-
GPRSize = P.isGP64bit() ? AFL_REG_64 : AFL_REG_32;
129+
GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
189130
}
190131

191132
template <class PredicateLibrary>
192133
void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
193134
if (P.abiUsesSoftFloat())
194-
CPR1Size = AFL_REG_NONE;
135+
CPR1Size = Mips::AFL_REG_NONE;
195136
else if (P.hasMSA())
196-
CPR1Size = AFL_REG_128;
137+
CPR1Size = Mips::AFL_REG_128;
197138
else
198-
CPR1Size = P.isFP64bit() ? AFL_REG_64 : AFL_REG_32;
139+
CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
199140
}
200141

201142
template <class PredicateLibrary>
202143
void setASESetFromPredicates(const PredicateLibrary &P) {
203144
ASESet = 0;
204145
if (P.hasDSP())
205-
ASESet |= AFL_ASE_DSP;
146+
ASESet |= Mips::AFL_ASE_DSP;
206147
if (P.hasDSPR2())
207-
ASESet |= AFL_ASE_DSPR2;
148+
ASESet |= Mips::AFL_ASE_DSPR2;
208149
if (P.hasMSA())
209-
ASESet |= AFL_ASE_MSA;
150+
ASESet |= Mips::AFL_ASE_MSA;
210151
if (P.inMicroMipsMode())
211-
ASESet |= AFL_ASE_MICROMIPS;
152+
ASESet |= Mips::AFL_ASE_MICROMIPS;
212153
if (P.inMips16Mode())
213-
ASESet |= AFL_ASE_MIPS16;
154+
ASESet |= Mips::AFL_ASE_MIPS16;
214155
}
215156

216157
template <class PredicateLibrary>

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