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ahmedbougachaahmedbougacha
committedJan 8, 2015
[SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
·
llvmorg-21-initllvmorg-3.6.0-rc1
1 parent c99cc19 commit 2b6917b

21 files changed

+246
-183
lines changed
 

Diff for: ‎llvm/include/llvm/Target/TargetLowering.h

+16-14
Original file line numberDiff line numberDiff line change
@@ -557,18 +557,19 @@ class TargetLoweringBase {
557557
/// Return how this load with extension should be treated: either it is legal,
558558
/// needs to be promoted to a larger size, needs to be expanded to some other
559559
/// code sequence, or the target has a custom expander for it.
560-
LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
561-
if (VT.isExtended()) return Expand;
562-
unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
563-
assert(ExtType < ISD::LAST_LOADEXT_TYPE && I < MVT::LAST_VALUETYPE &&
564-
"Table isn't big enough!");
565-
return (LegalizeAction)LoadExtActions[I][ExtType];
560+
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const {
561+
if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
562+
unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
563+
unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
564+
assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
565+
MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
566+
return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
566567
}
567568

568569
/// Return true if the specified load with extension is legal on this target.
569-
bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
570-
return VT.isSimple() &&
571-
getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
570+
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
571+
return ValVT.isSimple() && MemVT.isSimple() &&
572+
getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
572573
}
573574

574575
/// Return how this store with truncation should be treated: either it is
@@ -1237,11 +1238,11 @@ class TargetLoweringBase {
12371238

12381239
/// Indicate that the specified load with extension does not work with the
12391240
/// specified type and indicate what to do about it.
1240-
void setLoadExtAction(unsigned ExtType, MVT VT,
1241+
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
12411242
LegalizeAction Action) {
1242-
assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT.isValid() &&
1243-
"Table isn't big enough!");
1244-
LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1243+
assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1244+
MemVT.isValid() && "Table isn't big enough!");
1245+
LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
12451246
}
12461247

12471248
/// Indicate that the specified truncating store does not work with the
@@ -1737,7 +1738,8 @@ class TargetLoweringBase {
17371738
/// For each load extension type and each value type, keep a LegalizeAction
17381739
/// that indicates how instruction selection should deal with a load of a
17391740
/// specific value type and extension type.
1740-
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1741+
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1742+
[ISD::LAST_LOADEXT_TYPE];
17411743

17421744
/// For each value type pair keep a LegalizeAction that indicates whether a
17431745
/// truncating store of a specific value type and truncating type is legal.

Diff for: ‎llvm/lib/CodeGen/BasicTargetTransformInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,7 @@ unsigned BasicTTI::getMemoryOpCost(unsigned Opcode, Type *Src,
519519
if (Opcode == Instruction::Store)
520520
LA = getTLI()->getTruncStoreAction(LT.second, MemVT.getSimpleVT());
521521
else
522-
LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, MemVT.getSimpleVT());
522+
LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
523523
}
524524

525525
if (LA != TargetLowering::Legal && LA != TargetLowering::Custom) {

Diff for: ‎llvm/lib/CodeGen/CodeGenPrepare.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -3432,7 +3432,7 @@ bool CodeGenPrepare::MoveExtToFormExtLoad(Instruction *&I) {
34323432
assert(isa<SExtInst>(I) && "Unexpected ext type!");
34333433
LType = ISD::SEXTLOAD;
34343434
}
3435-
if (TLI && !TLI->isLoadExtLegal(LType, LoadVT)) {
3435+
if (TLI && !TLI->isLoadExtLegal(LType, VT, LoadVT)) {
34363436
I = OldExt;
34373437
TPT.rollback(LastKnownGood);
34383438
return false;

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+29-26
Original file line numberDiff line numberDiff line change
@@ -877,8 +877,8 @@ SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
877877
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
878878
EVT MemVT = LD->getMemoryVT();
879879
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
880-
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
881-
: ISD::EXTLOAD)
880+
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
881+
: ISD::EXTLOAD)
882882
: LD->getExtensionType();
883883
Replace = true;
884884
return DAG.getExtLoad(ExtType, dl, PVT,
@@ -1099,8 +1099,8 @@ bool DAGCombiner::PromoteLoad(SDValue Op) {
10991099
LoadSDNode *LD = cast<LoadSDNode>(N);
11001100
EVT MemVT = LD->getMemoryVT();
11011101
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1102-
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
1103-
: ISD::EXTLOAD)
1102+
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1103+
: ISD::EXTLOAD)
11041104
: LD->getExtensionType();
11051105
SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
11061106
LD->getChain(), LD->getBasePtr(),
@@ -2800,6 +2800,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
28002800
// actually legal and isn't going to get expanded, else this is a false
28012801
// optimisation.
28022802
bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2803+
Load->getValueType(0),
28032804
Load->getMemoryVT());
28042805

28052806
// Resize the constant to the same size as the original memory access before
@@ -2926,7 +2927,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
29262927
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
29272928
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
29282929
((!LegalOperations && !LN0->isVolatile()) ||
2929-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2930+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
29302931
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
29312932
LN0->getChain(), LN0->getBasePtr(),
29322933
MemVT, LN0->getMemOperand());
@@ -2946,7 +2947,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
29462947
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
29472948
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
29482949
((!LegalOperations && !LN0->isVolatile()) ||
2949-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2950+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
29502951
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
29512952
LN0->getChain(), LN0->getBasePtr(),
29522953
MemVT, LN0->getMemOperand());
@@ -2972,10 +2973,11 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
29722973
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
29732974
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
29742975
EVT LoadedVT = LN0->getMemoryVT();
2976+
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
29752977

29762978
if (ExtVT == LoadedVT &&
2977-
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2978-
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2979+
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2980+
ExtVT))) {
29792981

29802982
SDValue NewLoad =
29812983
DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
@@ -2990,7 +2992,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
29902992
// Do not generate loads of non-round integer types since these can
29912993
// be expensive (and would be wrong if the type is not byte sized).
29922994
if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2993-
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2995+
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2996+
ExtVT))) {
29942997
EVT PtrType = LN0->getOperand(1).getValueType();
29952998

29962999
unsigned Alignment = LN0->getAlignment();
@@ -3010,7 +3013,6 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
30103013

30113014
AddToWorklist(NewPtr.getNode());
30123015

3013-
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
30143016
SDValue Load =
30153017
DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
30163018
LN0->getChain(), NewPtr,
@@ -5282,7 +5284,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
52825284
if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
52835285
ISD::isUNINDEXEDLoad(N0.getNode()) &&
52845286
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5285-
TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
5287+
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
52865288
bool DoXform = true;
52875289
SmallVector<SDNode*, 4> SetCCs;
52885290
if (!N0.hasOneUse())
@@ -5310,7 +5312,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
53105312
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
53115313
EVT MemVT = LN0->getMemoryVT();
53125314
if ((!LegalOperations && !LN0->isVolatile()) ||
5313-
TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
5315+
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
53145316
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
53155317
LN0->getChain(),
53165318
LN0->getBasePtr(), MemVT,
@@ -5330,7 +5332,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
53305332
N0.getOpcode() == ISD::XOR) &&
53315333
isa<LoadSDNode>(N0.getOperand(0)) &&
53325334
N0.getOperand(1).getOpcode() == ISD::Constant &&
5333-
TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
5335+
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
53345336
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
53355337
LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
53365338
if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
@@ -5572,7 +5574,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
55725574
if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
55735575
ISD::isUNINDEXEDLoad(N0.getNode()) &&
55745576
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5575-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
5577+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
55765578
bool DoXform = true;
55775579
SmallVector<SDNode*, 4> SetCCs;
55785580
if (!N0.hasOneUse())
@@ -5600,7 +5602,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
56005602
N0.getOpcode() == ISD::XOR) &&
56015603
isa<LoadSDNode>(N0.getOperand(0)) &&
56025604
N0.getOperand(1).getOpcode() == ISD::Constant &&
5603-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
5605+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
56045606
(!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
56055607
LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
56065608
if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
@@ -5637,7 +5639,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
56375639
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
56385640
EVT MemVT = LN0->getMemoryVT();
56395641
if ((!LegalOperations && !LN0->isVolatile()) ||
5640-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
5642+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
56415643
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
56425644
LN0->getChain(),
56435645
LN0->getBasePtr(), MemVT,
@@ -5799,7 +5801,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
57995801
// scalars.
58005802
if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
58015803
ISD::isUNINDEXEDLoad(N0.getNode()) &&
5802-
TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
5804+
TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
58035805
bool DoXform = true;
58045806
SmallVector<SDNode*, 4> SetCCs;
58055807
if (!N0.hasOneUse())
@@ -5829,7 +5831,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
58295831
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
58305832
ISD::LoadExtType ExtType = LN0->getExtensionType();
58315833
EVT MemVT = LN0->getMemoryVT();
5832-
if (!LegalOperations || TLI.isLoadExtLegal(ExtType, MemVT)) {
5834+
if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
58335835
SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
58345836
VT, LN0->getChain(), LN0->getBasePtr(),
58355837
MemVT, LN0->getMemOperand());
@@ -5958,7 +5960,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
59585960
ExtVT = EVT::getIntegerVT(*DAG.getContext(),
59595961
VT.getSizeInBits() - N01->getZExtValue());
59605962
}
5961-
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5963+
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
59625964
return SDValue();
59635965

59645966
unsigned EVTBits = ExtVT.getSizeInBits();
@@ -6165,7 +6167,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
61656167
ISD::isUNINDEXEDLoad(N0.getNode()) &&
61666168
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
61676169
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6168-
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
6170+
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
61696171
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
61706172
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
61716173
LN0->getChain(),
@@ -6181,7 +6183,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
61816183
N0.hasOneUse() &&
61826184
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
61836185
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6184-
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
6186+
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
61856187
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
61866188
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
61876189
LN0->getChain(),
@@ -7726,7 +7728,7 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
77267728

77277729
// fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
77287730
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7729-
TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
7731+
TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
77307732
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
77317733
SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
77327734
LN0->getChain(),
@@ -10003,9 +10005,9 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
1000310005
EVT LegalizedStoredValueTy =
1000410006
TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
1000510007
if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10006-
TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
10007-
TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
10008-
TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
10008+
TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10009+
TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10010+
TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy))
1000910011
LastLegalIntegerType = i+1;
1001010012
}
1001110013
}
@@ -10443,7 +10445,8 @@ SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
1044310445
if (ResultVT.bitsGT(VecEltVT)) {
1044410446
// If the result type of vextract is wider than the load, then issue an
1044510447
// extending load instead.
10446-
ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT)
10448+
ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
10449+
VecEltVT)
1044710450
? ISD::ZEXTLOAD
1044810451
: ISD::EXTLOAD;
1044910452
Load = DAG.getExtLoad(

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

+7-4
Original file line numberDiff line numberDiff line change
@@ -260,7 +260,7 @@ SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
260260
if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261261
// Only do this if the target has a native EXTLOAD instruction from
262262
// smaller type.
263-
TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
263+
TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264264
TLI.ShouldShrinkFPConstant(OrigVT)) {
265265
Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266266
LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
@@ -944,7 +944,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
944944
// nice to have an effective generic way of getting these benefits...
945945
// Until such a way is found, don't insist on promoting i1 here.
946946
(SrcVT != MVT::i1 ||
947-
TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
947+
TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
948+
TargetLowering::Promote)) {
948949
// Promote to a byte-sized load if not loading an integral number of
949950
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
950951
unsigned NewWidth = SrcVT.getStoreSizeInBits();
@@ -1056,7 +1057,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
10561057
Chain = Ch;
10571058
} else {
10581059
bool isCustom = false;
1059-
switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1060+
switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1061+
SrcVT.getSimpleVT())) {
10601062
default: llvm_unreachable("This action is not supported yet!");
10611063
case TargetLowering::Custom:
10621064
isCustom = true;
@@ -1088,7 +1090,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
10881090
break;
10891091
}
10901092
case TargetLowering::Expand:
1091-
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1093+
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0),
1094+
SrcVT) && TLI.isTypeLegal(SrcVT)) {
10921095
SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr, LD->getMemOperand());
10931096
unsigned ExtendOp;
10941097
switch (ExtType) {

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
200200
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
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switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getMemoryVT())) {
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switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
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LD->getMemoryVT())) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);

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