@@ -178,38 +178,6 @@ class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
178
178
let mayStore = 1;
179
179
}
180
180
181
- class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
182
- SDPatternOperator OpNode= null_frag> :
183
- InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
184
- [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
185
- let DecoderMethod = "DecodeFMem2";
186
- let mayStore = 1;
187
- }
188
-
189
- class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
190
- SDPatternOperator OpNode= null_frag> :
191
- InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
192
- [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
193
- let DecoderMethod = "DecodeFMem2";
194
- let mayLoad = 1;
195
- }
196
-
197
- class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
198
- SDPatternOperator OpNode= null_frag> :
199
- InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
200
- [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
201
- let DecoderMethod = "DecodeFMem3";
202
- let mayStore = 1;
203
- }
204
-
205
- class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
206
- SDPatternOperator OpNode= null_frag> :
207
- InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
208
- [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
209
- let DecoderMethod = "DecodeFMem3";
210
- let mayLoad = 1;
211
- }
212
-
213
181
class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
214
182
SDPatternOperator OpNode = null_frag> :
215
183
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
@@ -436,30 +404,6 @@ def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
436
404
def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
437
405
ISA_MIPS2, FGR_32;
438
406
439
- // Cop2 Memory Instructions
440
- // FIXME: These aren't really FPU instructions and as such don't belong in this
441
- // file
442
- def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
443
- ISA_MIPS1_NOT_32R6_64R6;
444
- def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
445
- ISA_MIPS1_NOT_32R6_64R6;
446
- def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
447
- ISA_MIPS2_NOT_32R6_64R6;
448
- def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
449
- ISA_MIPS2_NOT_32R6_64R6;
450
-
451
- // Cop3 Memory Instructions
452
- // FIXME: These aren't really FPU instructions and as such don't belong in this
453
- // file
454
- let DecoderNamespace = "COP3_" in {
455
- def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
456
- def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
457
- def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
458
- ISA_MIPS2;
459
- def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
460
- ISA_MIPS2;
461
- }
462
-
463
407
// Indexed loads and stores.
464
408
// Base register + offset register addressing mode (indicated by "x" in the
465
409
// instruction mnemonic) is disallowed under NaCl.
0 commit comments