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Vasileios KalintirisVasileios Kalintiris
Vasileios Kalintiris
authored and
Vasileios Kalintiris
committedNov 4, 2014
[mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to MipsInstrInfo.td. NFC.
Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5843 llvm-svn: 221300
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‎llvm/lib/Target/Mips/MipsInstrFPU.td

Lines changed: 0 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -178,38 +178,6 @@ class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
178178
let mayStore = 1;
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}
180180

181-
class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
183-
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
184-
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
185-
let DecoderMethod = "DecodeFMem2";
186-
let mayStore = 1;
187-
}
188-
189-
class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
191-
InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem2";
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let mayLoad = 1;
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}
196-
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class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
199-
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
200-
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
201-
let DecoderMethod = "DecodeFMem3";
202-
let mayStore = 1;
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}
204-
205-
class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem3";
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let mayLoad = 1;
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}
212-
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class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
215183
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
@@ -436,30 +404,6 @@ def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
436404
def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
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ISA_MIPS2, FGR_32;
438406

439-
// Cop2 Memory Instructions
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// FIXME: These aren't really FPU instructions and as such don't belong in this
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// file
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def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
443-
ISA_MIPS1_NOT_32R6_64R6;
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def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
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ISA_MIPS1_NOT_32R6_64R6;
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def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
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ISA_MIPS2_NOT_32R6_64R6;
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def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
449-
ISA_MIPS2_NOT_32R6_64R6;
450-
451-
// Cop3 Memory Instructions
452-
// FIXME: These aren't really FPU instructions and as such don't belong in this
453-
// file
454-
let DecoderNamespace = "COP3_" in {
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def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
456-
def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
457-
def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
458-
ISA_MIPS2;
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def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
460-
ISA_MIPS2;
461-
}
462-
463407
// Indexed loads and stores.
464408
// Base register + offset register addressing mode (indicated by "x" in the
465409
// instruction mnemonic) is disallowed under NaCl.

‎llvm/lib/Target/Mips/MipsInstrInfo.td

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -672,6 +672,40 @@ class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
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let DecoderMethod = "DecodeMem";
673673
}
674674

675+
// COP2 Load/Store
676+
class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
677+
SDPatternOperator OpNode= null_frag> :
678+
InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
679+
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
680+
let DecoderMethod = "DecodeFMem2";
681+
let mayLoad = 1;
682+
}
683+
684+
class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
685+
SDPatternOperator OpNode= null_frag> :
686+
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
687+
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
688+
let DecoderMethod = "DecodeFMem2";
689+
let mayStore = 1;
690+
}
691+
692+
// COP3 Load/Store
693+
class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
694+
SDPatternOperator OpNode= null_frag> :
695+
InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
696+
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
697+
let DecoderMethod = "DecodeFMem3";
698+
let mayLoad = 1;
699+
}
700+
701+
class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
702+
SDPatternOperator OpNode= null_frag> :
703+
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
704+
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
705+
let DecoderMethod = "DecodeFMem3";
706+
let mayStore = 1;
707+
}
708+
675709
// Conditional Branch
676710
class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
677711
RegisterOperand RO, bit DelaySlot = 1> :
@@ -1150,6 +1184,26 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
11501184
ISA_MIPS1_NOT_32R6_64R6;
11511185
}
11521186

1187+
// COP2 Memory Instructions
1188+
def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1189+
ISA_MIPS1_NOT_32R6_64R6;
1190+
def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1191+
ISA_MIPS1_NOT_32R6_64R6;
1192+
def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1193+
ISA_MIPS2_NOT_32R6_64R6;
1194+
def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1195+
ISA_MIPS2_NOT_32R6_64R6;
1196+
1197+
// COP3 Memory Instructions
1198+
let DecoderNamespace = "COP3_" in {
1199+
def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1200+
def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1201+
def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1202+
ISA_MIPS2;
1203+
def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1204+
ISA_MIPS2;
1205+
}
1206+
11531207
def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
11541208

11551209
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;

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