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Commit b0852e5

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author
Zoran Jovanovic
committedOct 21, 2014
[mips][microMIPS] Implement microMIPS 16-bit instructions registers
Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
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3 files changed

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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+19
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,14 @@ class MipsOperand : public MCParsedAsmOperand {
492492
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
493493
}
494494

495+
/// Coerce the register to GPR32 and return the real register for the current
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/// target.
497+
unsigned getGPRMM16Reg() const {
498+
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
499+
unsigned ClassID = Mips::GPR32RegClassID;
500+
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
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}
502+
495503
/// Coerce the register to GPR64 and return the real register for the current
496504
/// target.
497505
unsigned getGPR64Reg() const {
@@ -640,6 +648,11 @@ class MipsOperand : public MCParsedAsmOperand {
640648
Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
641649
}
642650

651+
void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
653+
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
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}
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/// Render the operand to an MCInst as a GPR64
644657
/// Asserts if the wrong number of operands are requested, or the operand
645658
/// is not a k_RegisterIndex compatible with RegKind_GPR
@@ -900,6 +913,12 @@ class MipsOperand : public MCParsedAsmOperand {
900913
bool isGPRAsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
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}
916+
bool isMM16AsmReg() const {
917+
if (!(isRegIdx() && RegIdx.Kind))
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return false;
919+
return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
920+
|| RegIdx.Index == 16 || RegIdx.Index == 17);
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}
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bool isFGRAsmReg() const {
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// AFGR64 is $0-$15 but we handle this in getAFGR64()
905924
return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;

‎llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

+12
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,11 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
117117
uint64_t Address,
118118
const void *Decoder);
119119

120+
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
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unsigned RegNo,
122+
uint64_t Address,
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const void *Decoder);
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120125
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
@@ -870,6 +875,13 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
872877

878+
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
881+
const void *Decoder) {
882+
return MCDisassembler::Fail;
883+
}
884+
873885
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
874886
unsigned RegNo,
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uint64_t Address,

‎llvm/lib/Target/Mips/MipsRegisterInfo.td

+15
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,12 @@ class GPR32Class<list<ValueType> regTypes> :
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def GPR32 : GPR32Class<[i32]>;
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def DSPR : GPR32Class<[v4i8, v2i16]>;
285285

286+
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
287+
// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Callee save
290+
S0, S1)>;
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286292
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
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// Reserved
288294
ZERO_64, AT_64,
@@ -430,6 +436,11 @@ def GPR32AsmOperand : MipsAsmRegOperand {
430436
let PredicateMethod = "isGPRAsmReg";
431437
}
432438

439+
def GPRMM16AsmOperand : MipsAsmRegOperand {
440+
let Name = "GPRMM16AsmReg";
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let PredicateMethod = "isMM16AsmReg";
442+
}
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433444
def ACC64DSPAsmOperand : MipsAsmRegOperand {
434445
let Name = "ACC64DSPAsmReg";
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let PredicateMethod = "isACCAsmReg";
@@ -485,6 +496,10 @@ def GPR32Opnd : RegisterOperand<GPR32> {
485496
let ParserMatchClass = GPR32AsmOperand;
486497
}
487498

499+
def GPRMM16Opnd : RegisterOperand<GPRMM16> {
500+
let ParserMatchClass = GPRMM16AsmOperand;
501+
}
502+
488503
def GPR64Opnd : RegisterOperand<GPR64> {
489504
let ParserMatchClass = GPR64AsmOperand;
490505
}

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