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Vasileios KalintirisVasileios Kalintiris
Vasileios Kalintiris
authored and
Vasileios Kalintiris
committedOct 16, 2014
[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Summary: In order to support big endian targets for the BuildPairF64 nodes we just need to swap the low/high pair registers. Additionally, for the ExtractElementF64 nodes we have to calculate the correct stack offset with respect to the node's register/operand that we want to extract. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5753 llvm-svn: 219931
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Diff for: ‎llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

+4-1
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,8 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
325325
// We re-use the same spill slot each time so that the stack frame doesn't
326326
// grow too much in functions with a large number of moves.
327327
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
328+
if (!Subtarget.isLittle())
329+
std::swap(LoReg, HiReg);
328330
TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
329331
0);
330332
TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
@@ -369,6 +371,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
369371
unsigned DstReg = I->getOperand(0).getReg();
370372
unsigned SrcReg = I->getOperand(1).getReg();
371373
unsigned N = I->getOperand(2).getImm();
374+
int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
372375

373376
// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
374377
// the cases where mfhc1 is not available). 64-bit architectures and
@@ -385,7 +388,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
385388
int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
386389
TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
387390
0);
388-
TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4);
391+
TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset);
389392
return true;
390393
}
391394

Diff for: ‎llvm/test/CodeGen/Mips/fp64a.ll

+31-67
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@
1212
; this check here.
1313

1414
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE
15-
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-BE
15+
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
1616
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE
17-
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-LE
17+
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
1818

1919
; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A
2020
; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
@@ -38,15 +38,10 @@ define double @call1(double %d, ...) {
3838
; 32R2-NO-FP64A-BE: mtc1 $5, $f0
3939
; 32R2-NO-FP64A-BE: mthc1 $4, $f0
4040

41-
; 32R2-FP64A-LE: addiu $sp, $sp, -8
42-
; 32R2-FP64A-LE: sw $4, 0($sp)
43-
; 32R2-FP64A-LE: sw $5, 4($sp)
44-
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
45-
46-
; 32R2-FP64A-BE: addiu $sp, $sp, -8
47-
; 32R2-FP64A-BE: sw $5, 0($sp)
48-
; 32R2-FP64A-BE: sw $4, 4($sp)
49-
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
41+
; 32R2-FP64A: addiu $sp, $sp, -8
42+
; 32R2-FP64A: sw $4, 0($sp)
43+
; 32R2-FP64A: sw $5, 4($sp)
44+
; 32R2-FP64A: ldc1 $f0, 0($sp)
5045

5146
; 64-NO-FP64A: daddiu $sp, $sp, -64
5247
; 64-NO-FP64A: mov.d $f0, $f12
@@ -63,15 +58,10 @@ define double @call2(i32 %i, double %d) {
6358
; 32R2-NO-FP64A-BE: mtc1 $7, $f0
6459
; 32R2-NO-FP64A-BE: mthc1 $6, $f0
6560

66-
; 32R2-FP64A-LE: addiu $sp, $sp, -8
67-
; 32R2-FP64A-LE: sw $6, 0($sp)
68-
; 32R2-FP64A-LE: sw $7, 4($sp)
69-
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
70-
71-
; 32R2-FP64A-BE: addiu $sp, $sp, -8
72-
; 32R2-FP64A-BE: sw $7, 0($sp)
73-
; 32R2-FP64A-BE: sw $6, 4($sp)
74-
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
61+
; 32R2-FP64A: addiu $sp, $sp, -8
62+
; 32R2-FP64A: sw $6, 0($sp)
63+
; 32R2-FP64A: sw $7, 4($sp)
64+
; 32R2-FP64A: ldc1 $f0, 0($sp)
7565

7666
; 64-NO-FP64A-NOT: daddiu $sp, $sp
7767
; 64-NO-FP64A: mov.d $f0, $f13
@@ -88,15 +78,10 @@ define double @call3(float %f1, float %f2, double %d) {
8878
; 32R2-NO-FP64A-BE: mtc1 $7, $f0
8979
; 32R2-NO-FP64A-BE: mthc1 $6, $f0
9080

91-
; 32R2-FP64A-LE: addiu $sp, $sp, -8
92-
; 32R2-FP64A-LE: sw $6, 0($sp)
93-
; 32R2-FP64A-LE: sw $7, 4($sp)
94-
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
95-
96-
; 32R2-FP64A-BE: addiu $sp, $sp, -8
97-
; 32R2-FP64A-BE: sw $7, 0($sp)
98-
; 32R2-FP64A-BE: sw $6, 4($sp)
99-
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
81+
; 32R2-FP64A: addiu $sp, $sp, -8
82+
; 32R2-FP64A: sw $6, 0($sp)
83+
; 32R2-FP64A: sw $7, 4($sp)
84+
; 32R2-FP64A: ldc1 $f0, 0($sp)
10085

10186
; 64-NO-FP64A-NOT: daddiu $sp, $sp
10287
; 64-NO-FP64A: mov.d $f0, $f14
@@ -113,15 +98,10 @@ define double @call4(float %f, double %d, ...) {
11398
; 32R2-NO-FP64A-BE: mtc1 $7, $f0
11499
; 32R2-NO-FP64A-BE: mthc1 $6, $f0
115100

116-
; 32R2-FP64A-LE: addiu $sp, $sp, -8
117-
; 32R2-FP64A-LE: sw $6, 0($sp)
118-
; 32R2-FP64A-LE: sw $7, 4($sp)
119-
; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
120-
121-
; 32R2-FP64A-BE: addiu $sp, $sp, -8
122-
; 32R2-FP64A-BE: sw $7, 0($sp)
123-
; 32R2-FP64A-BE: sw $6, 4($sp)
124-
; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
101+
; 32R2-FP64A: addiu $sp, $sp, -8
102+
; 32R2-FP64A: sw $6, 0($sp)
103+
; 32R2-FP64A: sw $7, 4($sp)
104+
; 32R2-FP64A: ldc1 $f0, 0($sp)
125105

126106
; 64-NO-FP64A: daddiu $sp, $sp, -48
127107
; 64-NO-FP64A: mov.d $f0, $f13
@@ -145,23 +125,14 @@ define double @call5(double %a, double %b, ...) {
145125
; 32R2-NO-FP64A-BE-DAG: mthc1 $6, $[[T1:f[0-9]+]]
146126
; 32R2-NO-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
147127

148-
; 32R2-FP64A-LE: addiu $sp, $sp, -8
149-
; 32R2-FP64A-LE: sw $6, 0($sp)
150-
; 32R2-FP64A-LE: sw $7, 4($sp)
151-
; 32R2-FP64A-LE: ldc1 $[[T1:f[0-9]+]], 0($sp)
152-
; 32R2-FP64A-LE: sw $4, 0($sp)
153-
; 32R2-FP64A-LE: sw $5, 4($sp)
154-
; 32R2-FP64A-LE: ldc1 $[[T0:f[0-9]+]], 0($sp)
155-
; 32R2-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]]
156-
157-
; 32R2-FP64A-BE: addiu $sp, $sp, -8
158-
; 32R2-FP64A-BE: sw $7, 0($sp)
159-
; 32R2-FP64A-BE: sw $6, 4($sp)
160-
; 32R2-FP64A-BE: ldc1 $[[T1:f[0-9]+]], 0($sp)
161-
; 32R2-FP64A-BE: sw $5, 0($sp)
162-
; 32R2-FP64A-BE: sw $4, 4($sp)
163-
; 32R2-FP64A-BE: ldc1 $[[T0:f[0-9]+]], 0($sp)
164-
; 32R2-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
128+
; 32R2-FP64A: addiu $sp, $sp, -8
129+
; 32R2-FP64A: sw $6, 0($sp)
130+
; 32R2-FP64A: sw $7, 4($sp)
131+
; 32R2-FP64A: ldc1 $[[T1:f[0-9]+]], 0($sp)
132+
; 32R2-FP64A: sw $4, 0($sp)
133+
; 32R2-FP64A: sw $5, 4($sp)
134+
; 32R2-FP64A: ldc1 $[[T0:f[0-9]+]], 0($sp)
135+
; 32R2-FP64A: sub.d $f0, $[[T0]], $[[T1]]
165136

166137
; 64-NO-FP64A: sub.d $f0, $f12, $f13
167138
}
@@ -179,19 +150,12 @@ define double @move_from(double %d) {
179150
; 32R2-NO-FP64A-BE-DAG: mfc1 $7, $f0
180151
; 32R2-NO-FP64A-BE-DAG: mfhc1 $6, $f0
181152

182-
; 32R2-FP64A-LE: addiu $sp, $sp, -32
183-
; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
184-
; 32R2-FP64A-LE: lw $6, 16($sp)
185-
; FIXME: This store is redundant
186-
; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
187-
; 32R2-FP64A-LE: lw $7, 20($sp)
188-
189-
; 32R2-FP64A-BE: addiu $sp, $sp, -32
190-
; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
191-
; 32R2-FP64A-BE: lw $6, 20($sp)
153+
; 32R2-FP64A: addiu $sp, $sp, -32
154+
; 32R2-FP64A: sdc1 $f0, 16($sp)
155+
; 32R2-FP64A: lw $6, 16($sp)
192156
; FIXME: This store is redundant
193-
; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
194-
; 32R2-FP64A-BE: lw $7, 16($sp)
157+
; 32R2-FP64A: sdc1 $f0, 16($sp)
158+
; 32R2-FP64A: lw $7, 20($sp)
195159

196160
; 64-NO-FP64A: mov.d $f13, $f0
197161
}

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