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dsandersllvmdsandersllvm
committedJun 16, 2014
[mips] Merge most of the big/little endian checks in atomic.ll
Summary: There is very little difference between the big and little endian cases in test/CodeGen/Mips/atomic.ll. Merge them together using multiple FileCheck prefixes. Depends on D4117 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4118 llvm-svn: 211013
·
llvmorg-21-initllvmorg-3.5.0-rc1
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‎llvm/test/CodeGen/Mips/atomic.ll

+179-333
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EL
2-
; RUN: llc -march=mips --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EB
1+
; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s -check-prefix=ALL -check-prefix=CHECK-EL
2+
; RUN: llc -march=mips --disable-machine-licm < %s | FileCheck %s -check-prefix=ALL -check-prefix=CHECK-EB
33

44
@x = common global i32 0, align 4
55

@@ -8,45 +8,30 @@ entry:
88
%0 = atomicrmw add i32* @x, i32 %incr monotonic
99
ret i32 %0
1010

11-
; CHECK-EL-LABEL: AtomicLoadAdd32:
12-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
13-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
14-
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
15-
; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4
16-
; CHECK-EL: sc $[[R2]], 0($[[R0]])
17-
; CHECK-EL: beqz $[[R2]], $[[BB0]]
18-
19-
; CHECK-EB-LABEL: AtomicLoadAdd32:
20-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
21-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
22-
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
23-
; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4
24-
; CHECK-EB: sc $[[R2]], 0($[[R0]])
25-
; CHECK-EB: beqz $[[R2]], $[[BB0]]
11+
; ALL-LABEL: AtomicLoadAdd32:
12+
13+
; ALL: lw $[[R0:[0-9]+]], %got(x)
14+
; ALL: $[[BB0:[A-Z_0-9]+]]:
15+
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
16+
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
17+
; ALL: sc $[[R2]], 0($[[R0]])
18+
; ALL: beqz $[[R2]], $[[BB0]]
2619
}
2720

2821
define i32 @AtomicLoadNand32(i32 %incr) nounwind {
2922
entry:
3023
%0 = atomicrmw nand i32* @x, i32 %incr monotonic
3124
ret i32 %0
3225

33-
; CHECK-EL-LABEL: AtomicLoadNand32:
34-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
35-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
36-
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
37-
; CHECK-EL: and $[[R3:[0-9]+]], $[[R1]], $4
38-
; CHECK-EL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
39-
; CHECK-EL: sc $[[R2]], 0($[[R0]])
40-
; CHECK-EL: beqz $[[R2]], $[[BB0]]
41-
42-
; CHECK-EB-LABEL: AtomicLoadNand32:
43-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
44-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
45-
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
46-
; CHECK-EB: and $[[R3:[0-9]+]], $[[R1]], $4
47-
; CHECK-EB: nor $[[R2:[0-9]+]], $zero, $[[R3]]
48-
; CHECK-EB: sc $[[R2]], 0($[[R0]])
49-
; CHECK-EB: beqz $[[R2]], $[[BB0]]
26+
; ALL-LABEL: AtomicLoadNand32:
27+
28+
; ALL: lw $[[R0:[0-9]+]], %got(x)
29+
; ALL: $[[BB0:[A-Z_0-9]+]]:
30+
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
31+
; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
32+
; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
33+
; ALL: sc $[[R2]], 0($[[R0]])
34+
; ALL: beqz $[[R2]], $[[BB0]]
5035
}
5136

5237
define i32 @AtomicSwap32(i32 %newval) nounwind {
@@ -57,19 +42,13 @@ entry:
5742
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
5843
ret i32 %0
5944

60-
; CHECK-EL-LABEL: AtomicSwap32:
61-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
62-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
63-
; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])
64-
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
65-
; CHECK-EL: beqz $[[R2]], $[[BB0]]
66-
67-
; CHECK-EB-LABEL: AtomicSwap32:
68-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
69-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
70-
; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])
71-
; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
72-
; CHECK-EB: beqz $[[R2]], $[[BB0]]
45+
; ALL-LABEL: AtomicSwap32:
46+
47+
; ALL: lw $[[R0:[0-9]+]], %got(x)
48+
; ALL: $[[BB0:[A-Z_0-9]+]]:
49+
; ALL: ll ${{[0-9]+}}, 0($[[R0]])
50+
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
51+
; ALL: beqz $[[R2]], $[[BB0]]
7352
}
7453

7554
define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
@@ -81,23 +60,15 @@ entry:
8160
%1 = extractvalue { i32, i1 } %0, 0
8261
ret i32 %1
8362

84-
; CHECK-EL-LABEL: AtomicCmpSwap32:
85-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
86-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
87-
; CHECK-EL: ll $2, 0($[[R0]])
88-
; CHECK-EL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
89-
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
90-
; CHECK-EL: beqz $[[R2]], $[[BB0]]
91-
; CHECK-EL: $[[BB1]]:
92-
93-
; CHECK-EB-LABEL: AtomicCmpSwap32:
94-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
95-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
96-
; CHECK-EB: ll $2, 0($[[R0]])
97-
; CHECK-EB: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
98-
; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
99-
; CHECK-EB: beqz $[[R2]], $[[BB0]]
100-
; CHECK-EB: $[[BB1]]:
63+
; ALL-LABEL: AtomicCmpSwap32:
64+
65+
; ALL: lw $[[R0:[0-9]+]], %got(x)
66+
; ALL: $[[BB0:[A-Z_0-9]+]]:
67+
; ALL: ll $2, 0($[[R0]])
68+
; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
69+
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
70+
; ALL: beqz $[[R2]], $[[BB0]]
71+
; ALL: $[[BB1]]:
10172
}
10273

10374

@@ -109,227 +80,135 @@ entry:
10980
%0 = atomicrmw add i8* @y, i8 %incr monotonic
11081
ret i8 %0
11182

112-
; CHECK-EL-LABEL: AtomicLoadAdd8:
113-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
114-
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
115-
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
116-
; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3
117-
; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3
118-
; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255
119-
; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
120-
; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]
121-
; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
122-
123-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
124-
; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
125-
; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
126-
; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
127-
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
128-
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
129-
; CHECK-EL: sc $[[R14]], 0($[[R2]])
130-
; CHECK-EL: beqz $[[R14]], $[[BB0]]
131-
132-
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
133-
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
134-
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
135-
; CHECK-EL: sra $2, $[[R17]], 24
136-
137-
; CHECK-EB-LABEL: AtomicLoadAdd8:
138-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
139-
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
140-
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
141-
; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3
142-
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
143-
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
144-
; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255
145-
; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
146-
; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]
147-
; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
148-
149-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
150-
; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])
151-
; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
152-
; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
153-
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
154-
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
155-
; CHECK-EB: sc $[[R14]], 0($[[R2]])
156-
; CHECK-EB: beqz $[[R14]], $[[BB0]]
157-
158-
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
159-
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
160-
; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24
161-
; CHECK-EB: sra $2, $[[R17]], 24
83+
; ALL-LABEL: AtomicLoadAdd8:
84+
85+
; ALL: lw $[[R0:[0-9]+]], %got(y)
86+
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
87+
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
88+
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
89+
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
90+
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
91+
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
92+
; ALL: ori $[[R6:[0-9]+]], $zero, 255
93+
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
94+
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
95+
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
96+
97+
; ALL: $[[BB0:[A-Z_0-9]+]]:
98+
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
99+
; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
100+
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
101+
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
102+
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
103+
; ALL: sc $[[R14]], 0($[[R2]])
104+
; ALL: beqz $[[R14]], $[[BB0]]
105+
106+
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
107+
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
108+
; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24
109+
; ALL: sra $2, $[[R17]], 24
162110
}
163111

164112
define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
165113
entry:
166114
%0 = atomicrmw sub i8* @y, i8 %incr monotonic
167115
ret i8 %0
168116

169-
; CHECK-EL-LABEL: AtomicLoadSub8:
170-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
171-
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
172-
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
173-
; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3
174-
; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3
175-
; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255
176-
; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
177-
; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]
178-
; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
179-
180-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
181-
; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
182-
; CHECK-EL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
183-
; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
184-
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
185-
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
186-
; CHECK-EL: sc $[[R14]], 0($[[R2]])
187-
; CHECK-EL: beqz $[[R14]], $[[BB0]]
188-
189-
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
190-
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
191-
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
192-
; CHECK-EL: sra $2, $[[R17]], 24
193-
194-
; CHECK-EB-LABEL: AtomicLoadSub8:
195-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
196-
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
197-
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
198-
; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3
117+
; ALL-LABEL: AtomicLoadSub8:
118+
119+
; ALL: lw $[[R0:[0-9]+]], %got(y)
120+
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
121+
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
122+
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
123+
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
199124
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
200125
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
201-
; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255
202-
; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
203-
; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]
204-
; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
205-
206-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
207-
; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])
208-
; CHECK-EB: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
209-
; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
210-
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
211-
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
212-
; CHECK-EB: sc $[[R14]], 0($[[R2]])
213-
; CHECK-EB: beqz $[[R14]], $[[BB0]]
214-
215-
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
216-
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
217-
; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24
218-
; CHECK-EB: sra $2, $[[R17]], 24
126+
; ALL: ori $[[R6:[0-9]+]], $zero, 255
127+
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
128+
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
129+
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
130+
131+
; ALL: $[[BB0:[A-Z_0-9]+]]:
132+
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
133+
; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
134+
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
135+
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
136+
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
137+
; ALL: sc $[[R14]], 0($[[R2]])
138+
; ALL: beqz $[[R14]], $[[BB0]]
139+
140+
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
141+
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
142+
; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24
143+
; ALL: sra $2, $[[R17]], 24
219144
}
220145

221146
define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
222147
entry:
223148
%0 = atomicrmw nand i8* @y, i8 %incr monotonic
224149
ret i8 %0
225150

226-
; CHECK-EL-LABEL: AtomicLoadNand8:
227-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
228-
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
229-
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
230-
; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3
231-
; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3
232-
; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255
233-
; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
234-
; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]
235-
; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
236-
237-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
238-
; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
239-
; CHECK-EL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
240-
; CHECK-EL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
241-
; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
242-
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
243-
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
244-
; CHECK-EL: sc $[[R14]], 0($[[R2]])
245-
; CHECK-EL: beqz $[[R14]], $[[BB0]]
246-
247-
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
248-
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
249-
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
250-
; CHECK-EL: sra $2, $[[R17]], 24
251-
252-
; CHECK-EB-LABEL: AtomicLoadNand8:
253-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
254-
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
255-
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
256-
; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3
257-
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
258-
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
259-
; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255
260-
; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
261-
; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]
262-
; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
263-
264-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
265-
; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])
266-
; CHECK-EB: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
267-
; CHECK-EB: nor $[[R11:[0-9]+]], $zero, $[[R18]]
268-
; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
269-
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
270-
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
271-
; CHECK-EB: sc $[[R14]], 0($[[R2]])
272-
; CHECK-EB: beqz $[[R14]], $[[BB0]]
273-
274-
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
275-
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
276-
; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24
277-
; CHECK-EB: sra $2, $[[R17]], 24
151+
; ALL-LABEL: AtomicLoadNand8:
152+
153+
; ALL: lw $[[R0:[0-9]+]], %got(y)
154+
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
155+
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
156+
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
157+
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
158+
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
159+
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
160+
; ALL: ori $[[R6:[0-9]+]], $zero, 255
161+
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
162+
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
163+
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
164+
165+
; ALL: $[[BB0:[A-Z_0-9]+]]:
166+
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
167+
; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
168+
; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
169+
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
170+
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
171+
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
172+
; ALL: sc $[[R14]], 0($[[R2]])
173+
; ALL: beqz $[[R14]], $[[BB0]]
174+
175+
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
176+
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
177+
; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24
178+
; ALL: sra $2, $[[R17]], 24
278179
}
279180

280181
define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
281182
entry:
282183
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
283184
ret i8 %0
284185

285-
; CHECK-EL-LABEL: AtomicSwap8:
286-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
287-
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
288-
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
289-
; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3
290-
; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3
291-
; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255
292-
; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
293-
; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]
294-
; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
295-
296-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
297-
; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]])
298-
; CHECK-EL: and $[[R18:[0-9]+]], $[[R9]], $[[R6]]
299-
; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
300-
; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
301-
; CHECK-EL: sc $[[R14]], 0($[[R2]])
302-
; CHECK-EL: beqz $[[R14]], $[[BB0]]
303-
304-
; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
305-
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
306-
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
307-
; CHECK-EL: sra $2, $[[R17]], 24
308-
309-
; CHECK-EB-LABEL: AtomicSwap8:
310-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
311-
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
312-
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
313-
; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3
314-
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
315-
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
316-
; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255
317-
; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
318-
; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]
319-
; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
320-
321-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
322-
; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]])
323-
; CHECK-EB: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
324-
; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
325-
; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
326-
; CHECK-EB: sc $[[R14]], 0($[[R2]])
327-
; CHECK-EB: beqz $[[R14]], $[[BB0]]
328-
329-
; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
330-
; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
331-
; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24
332-
; CHECK-EB: sra $2, $[[R17]], 24
186+
; ALL-LABEL: AtomicSwap8:
187+
188+
; ALL: lw $[[R0:[0-9]+]], %got(y)
189+
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
190+
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
191+
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
192+
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
193+
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
194+
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
195+
; ALL: ori $[[R6:[0-9]+]], $zero, 255
196+
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
197+
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
198+
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
199+
200+
; ALL: $[[BB0:[A-Z_0-9]+]]:
201+
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
202+
; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
203+
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
204+
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
205+
; ALL: sc $[[R14]], 0($[[R2]])
206+
; ALL: beqz $[[R14]], $[[BB0]]
207+
208+
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
209+
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
210+
; ALL: sll $[[R17:[0-9]+]], $[[R16]], 24
211+
; ALL: sra $2, $[[R17]], 24
333212
}
334213

335214
define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
@@ -338,64 +217,37 @@ entry:
338217
%0 = extractvalue { i8, i1 } %pair0, 0
339218
ret i8 %0
340219

341-
; CHECK-EL-LABEL: AtomicCmpSwap8:
342-
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
343-
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
344-
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
345-
; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3
346-
; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3
347-
; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255
348-
; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
349-
; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]]
350-
; CHECK-EL: andi $[[R8:[0-9]+]], $4, 255
351-
; CHECK-EL: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
352-
; CHECK-EL: andi $[[R10:[0-9]+]], $5, 255
353-
; CHECK-EL: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]
354-
355-
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
356-
; CHECK-EL: ll $[[R12:[0-9]+]], 0($[[R2]])
357-
; CHECK-EL: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
358-
; CHECK-EL: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
359-
360-
; CHECK-EL: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
361-
; CHECK-EL: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
362-
; CHECK-EL: sc $[[R15]], 0($[[R2]])
363-
; CHECK-EL: beqz $[[R15]], $[[BB0]]
364-
365-
; CHECK-EL: $[[BB1]]:
366-
; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
367-
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
368-
; CHECK-EL: sra $2, $[[R17]], 24
369-
370-
; CHECK-EB-LABEL: AtomicCmpSwap8:
371-
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
372-
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
373-
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
374-
; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3
375-
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
376-
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
377-
; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255
378-
; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
379-
; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]]
380-
; CHECK-EB: andi $[[R9:[0-9]+]], $4, 255
381-
; CHECK-EB: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
382-
; CHECK-EB: andi $[[R11:[0-9]+]], $5, 255
383-
; CHECK-EB: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
384-
385-
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
386-
; CHECK-EB: ll $[[R13:[0-9]+]], 0($[[R2]])
387-
; CHECK-EB: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
388-
; CHECK-EB: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
389-
390-
; CHECK-EB: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
391-
; CHECK-EB: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
392-
; CHECK-EB: sc $[[R16]], 0($[[R2]])
393-
; CHECK-EB: beqz $[[R16]], $[[BB0]]
394-
395-
; CHECK-EB: $[[BB1]]:
396-
; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
397-
; CHECK-EB: sll $[[R18:[0-9]+]], $[[R17]], 24
398-
; CHECK-EB: sra $2, $[[R18]], 24
220+
; ALL-LABEL: AtomicCmpSwap8:
221+
222+
; ALL: lw $[[R0:[0-9]+]], %got(y)
223+
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
224+
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
225+
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
226+
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
227+
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
228+
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
229+
; ALL: ori $[[R6:[0-9]+]], $zero, 255
230+
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
231+
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
232+
; ALL: andi $[[R9:[0-9]+]], $4, 255
233+
; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
234+
; ALL: andi $[[R11:[0-9]+]], $5, 255
235+
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
236+
237+
; ALL: $[[BB0:[A-Z_0-9]+]]:
238+
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
239+
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
240+
; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
241+
242+
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
243+
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
244+
; ALL: sc $[[R16]], 0($[[R2]])
245+
; ALL: beqz $[[R16]], $[[BB0]]
246+
247+
; ALL: $[[BB1]]:
248+
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
249+
; ALL: sll $[[R18:[0-9]+]], $[[R17]], 24
250+
; ALL: sra $2, $[[R18]], 24
399251
}
400252

401253
@countsint = common global i32 0, align 4
@@ -405,19 +257,13 @@ entry:
405257
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
406258
ret i32 %0
407259

408-
; CHECK-EL-LABEL: CheckSync:
409-
; CHECK-EL: sync 0
410-
; CHECK-EL: ll
411-
; CHECK-EL: sc
412-
; CHECK-EL: beq
413-
; CHECK-EL: sync 0
414-
415-
; CHECK-EB-LABEL: CheckSync:
416-
; CHECK-EB: sync 0
417-
; CHECK-EB: ll
418-
; CHECK-EB: sc
419-
; CHECK-EB: beq
420-
; CHECK-EB: sync 0
260+
; ALL-LABEL: CheckSync:
261+
262+
; ALL: sync 0
263+
; ALL: ll
264+
; ALL: sc
265+
; ALL: beq
266+
; ALL: sync 0
421267
}
422268

423269
; make sure that this assertion in

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