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- ; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32
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- ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
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+ ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
2
+ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
3
+ ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6
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+ ; RUN: llc -march=mips -mcpu=mips32 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
5
+ ; RUN: llc -march=mips -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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+ ; RUN: llc -march=mips -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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+ ; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6
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+
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+ ; FIXME: The MIPS16 test should check its output
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; RUN: llc -march=mips -mcpu=mips16 < %s
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5
- ; 32: madd ${{[0-9]+}}
6
- ; DSP: madd $ac
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+ ; ALL-LABEL: madd1:
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+
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+ ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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+ ; 32-DAG: mtlo $6
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+ ; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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+ ; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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+ ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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+ ; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
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+ ; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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+ ; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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+
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+ ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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+ ; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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+ ; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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+ ; 64-DAG: daddu $2, $[[T2]], $[[T3]]
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+
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+ ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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+ ; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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+ ; 64R6-DAG: daddu $2, $[[T2]], $[[T3]]
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+
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define i64 @madd1 (i32 %a , i32 %b , i32 %c ) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
@@ -14,8 +54,47 @@ entry:
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ret i64 %add
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}
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- ; 32: maddu ${{[0-9]+}}
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- ; DSP: maddu $ac
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+ ; ALL-LABEL: madd2:
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+
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+ ; FIXME: We don't really need this instruction
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+ ; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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+ ; 32-DAG: mtlo $6
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+ ; 32-DAG: [[m:m]]addu ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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+ ; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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+ ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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+ ; FIXME: There's a redundant move here. We should remove it
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+ ; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $2, $[[T3]], $[[T2]]
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+
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+ ; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
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+ ; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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+ ; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
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+ ; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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+ ; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
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+ ; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
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+ ; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
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+ ; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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+ ; 64-DAG: daddu $2, $[[T4]], $[[T6]]
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+
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+ ; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
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+ ; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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+ ; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
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+ ; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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+ ; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
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+ ; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
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+ ; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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+ ; 64R6-DAG: daddu $2, $[[T4]], $[[T6]]
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+
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define i64 @madd2 (i32 %a , i32 %b , i32 %c ) nounwind readnone {
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entry:
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%conv = zext i32 %a to i64
@@ -26,8 +105,38 @@ entry:
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ret i64 %add
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}
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- ; 32: madd ${{[0-9]+}}
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- ; DSP: madd $ac
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+ ; ALL-LABEL: madd3:
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+
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+ ; 32-DAG: mthi $6
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+ ; 32-DAG: mtlo $7
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+ ; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: mtlo $[[AC]], $7
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+ ; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7
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+ ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
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+ ; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $6
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+ ; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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+
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+ ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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+ ; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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+ ; 64-DAG: daddu $2, $[[T2]], $6
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+
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+ ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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+ ; 64R6-DAG: daddu $2, $[[T2]], $6
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+
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define i64 @madd3 (i32 %a , i32 %b , i64 %c ) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
@@ -37,8 +146,41 @@ entry:
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ret i64 %add
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}
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- ; 32: msub ${{[0-9]+}}
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- ; DSP: msub $ac
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+ ; ALL-LABEL: msub1:
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+
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+ ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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+ ; 32-DAG: mtlo $6
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+ ; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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+ ; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
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+ ; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]
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+ ; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31
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+ ; 32R6-DAG: subu $2, $[[T5]], $[[T4]]
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+ ; 32R6-DAG: subu $3, $6, $[[T1]]
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+
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+ ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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+ ; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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+ ; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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+ ; 64-DAG: dsubu $2, $[[T3]], $[[T2]]
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+
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+ ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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+ ; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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+ ; 64R6-DAG: dsubu $2, $[[T3]], $[[T2]]
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+
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define i64 @msub1 (i32 %a , i32 %b , i32 %c ) nounwind readnone {
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entry:
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%conv = sext i32 %c to i64
@@ -49,8 +191,48 @@ entry:
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ret i64 %sub
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}
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- ; 32: msubu ${{[0-9]+}}
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- ; DSP: msubu $ac
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+ ; ALL-LABEL: msub2:
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+
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+ ; FIXME: We don't really need this instruction
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+ ; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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+ ; 32-DAG: mtlo $6
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+ ; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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+ ; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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+
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+ ; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
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+ ; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
214
+ ; 32R6-DAG: negu $2, $[[T3]]
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+ ; 32R6-DAG: subu $3, $6, $[[T1]]
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+
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+ ; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
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+ ; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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+ ; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
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+ ; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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+ ; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
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+ ; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
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+ ; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
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+ ; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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+ ; 64-DAG: dsubu $2, $[[T6]], $[[T4]]
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+
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+ ; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
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+ ; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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+ ; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
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+ ; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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+ ; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
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+ ; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
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+ ; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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+ ; 64R6-DAG: dsubu $2, $[[T6]], $[[T4]]
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+
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define i64 @msub2 (i32 %a , i32 %b , i32 %c ) nounwind readnone {
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entry:
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%conv = zext i32 %c to i64
@@ -61,8 +243,39 @@ entry:
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ret i64 %sub
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}
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- ; 32: msub ${{[0-9]+}}
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- ; DSP: msub $ac
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+ ; ALL-LABEL: msub3:
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+
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+ ; FIXME: We don't really need this instruction
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+ ; 32-DAG: mthi $6
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+ ; 32-DAG: mtlo $7
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+ ; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
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+ ; 32-DAG: [[m]]fhi $2
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+ ; 32-DAG: [[m]]flo $3
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+
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+ ; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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+ ; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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+ ; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
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+ ; DSP-DAG: mfhi $2, $[[AC]]
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+ ; DSP-DAG: mflo $3, $[[AC]]
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+
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+ ; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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+ ; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
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+ ; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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+ ; 32R6-DAG: subu $2, $6, $[[T3]]
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+ ; 32R6-DAG: subu $3, $7, $[[T1]]
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+
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+ ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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+ ; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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+ ; 64-DAG: dsubu $2, $6, $[[T2]]
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+
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+ ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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+ ; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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+ ; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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+ ; 64R6-DAG: dsubu $2, $6, $[[T2]]
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+
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define i64 @msub3 (i32 %a , i32 %b , i64 %c ) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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