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dsandersllvmdsandersllvm
committedJun 12, 2014
[mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6
Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
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‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ include "Mips32r6InstrFormats.td"
3636
// Removed: luxc1
3737
// Removed: lwxc1
3838
// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
39-
// Removed: madd, maddu, msub, msubu
4039
// Removed: movf, movt
4140
// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
4241
// Removed: movn, movz

‎llvm/lib/Target/Mips/MipsInstrInfo.td

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1247,10 +1247,14 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
12471247
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
12481248

12491249
// MADD*/MSUB*
1250-
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
1251-
def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
1252-
def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
1253-
def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
1250+
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1251+
ISA_MIPS32_NOT_32R6_64R6;
1252+
def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1253+
ISA_MIPS32_NOT_32R6_64R6;
1254+
def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1255+
ISA_MIPS32_NOT_32R6_64R6;
1256+
def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1257+
ISA_MIPS32_NOT_32R6_64R6;
12541258

12551259
let AdditionalPredicates = [NotDSP] in {
12561260
def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
@@ -1260,10 +1264,14 @@ def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
12601264
def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
12611265
def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
12621266
def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1263-
def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1264-
def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1265-
def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1266-
def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1267+
def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1268+
ISA_MIPS32_NOT_32R6_64R6;
1269+
def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1270+
ISA_MIPS32_NOT_32R6_64R6;
1271+
def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1272+
ISA_MIPS32_NOT_32R6_64R6;
1273+
def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1274+
ISA_MIPS32_NOT_32R6_64R6;
12671275
}
12681276

12691277
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,

‎llvm/lib/Target/Mips/MipsSEISelLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
155155
if (Subtarget->hasMips32r6()) {
156156
// MIPS32r6 replaces the accumulator-based multiplies with a three register
157157
// instruction
158+
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159+
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158160
setOperationAction(ISD::MUL, MVT::i32, Legal);
159161
setOperationAction(ISD::MULHS, MVT::i32, Legal);
160162
setOperationAction(ISD::MULHU, MVT::i32, Legal);
@@ -483,8 +485,8 @@ static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
483485
if (DCI.isBeforeLegalize())
484486
return SDValue();
485487

486-
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
487-
selectMADD(N, &DAG))
488+
if (Subtarget->hasMips32() && !Subtarget->hasMips32r6() &&
489+
N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
488490
return SDValue(N, 0);
489491

490492
return SDValue();

‎llvm/test/CodeGen/Mips/dsp-r1.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
1+
; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s
22

33
define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
44
entry:

‎llvm/test/CodeGen/Mips/madd-msub.ll

Lines changed: 227 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,49 @@
1-
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32
2-
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
1+
; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
2+
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
3+
; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6
4+
; RUN: llc -march=mips -mcpu=mips32 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
5+
; RUN: llc -march=mips -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
6+
; RUN: llc -march=mips -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
7+
; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6
8+
9+
; FIXME: The MIPS16 test should check its output
310
; RUN: llc -march=mips -mcpu=mips16 < %s
411

5-
; 32: madd ${{[0-9]+}}
6-
; DSP: madd $ac
12+
; ALL-LABEL: madd1:
13+
14+
; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
15+
; 32-DAG: mtlo $6
16+
; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
17+
; 32-DAG: [[m]]fhi $2
18+
; 32-DAG: [[m]]flo $3
19+
20+
; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
21+
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
22+
; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
23+
; DSP-DAG: mfhi $2, $[[AC]]
24+
; DSP-DAG: mflo $3, $[[AC]]
25+
26+
; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
27+
; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
28+
; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
29+
; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
30+
; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
31+
; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
32+
; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
33+
34+
; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
35+
; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
36+
; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
37+
; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
38+
; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
39+
; 64-DAG: daddu $2, $[[T2]], $[[T3]]
40+
41+
; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
42+
; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
43+
; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
44+
; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
45+
; 64R6-DAG: daddu $2, $[[T2]], $[[T3]]
46+
747
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
848
entry:
949
%conv = sext i32 %a to i64
@@ -14,8 +54,47 @@ entry:
1454
ret i64 %add
1555
}
1656

17-
; 32: maddu ${{[0-9]+}}
18-
; DSP: maddu $ac
57+
; ALL-LABEL: madd2:
58+
59+
; FIXME: We don't really need this instruction
60+
; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
61+
; 32-DAG: mtlo $6
62+
; 32-DAG: [[m:m]]addu ${{[45]}}, ${{[45]}}
63+
; 32-DAG: [[m]]fhi $2
64+
; 32-DAG: [[m]]flo $3
65+
66+
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
67+
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
68+
; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}}
69+
; DSP-DAG: mfhi $2, $[[AC]]
70+
; DSP-DAG: mflo $3, $[[AC]]
71+
72+
; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
73+
; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
74+
; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
75+
; FIXME: There's a redundant move here. We should remove it
76+
; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
77+
; 32R6-DAG: addu $2, $[[T3]], $[[T2]]
78+
79+
; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
80+
; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
81+
; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
82+
; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
83+
; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
84+
; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
85+
; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
86+
; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
87+
; 64-DAG: daddu $2, $[[T4]], $[[T6]]
88+
89+
; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
90+
; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
91+
; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
92+
; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
93+
; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
94+
; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
95+
; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
96+
; 64R6-DAG: daddu $2, $[[T4]], $[[T6]]
97+
1998
define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
2099
entry:
21100
%conv = zext i32 %a to i64
@@ -26,8 +105,38 @@ entry:
26105
ret i64 %add
27106
}
28107

29-
; 32: madd ${{[0-9]+}}
30-
; DSP: madd $ac
108+
; ALL-LABEL: madd3:
109+
110+
; 32-DAG: mthi $6
111+
; 32-DAG: mtlo $7
112+
; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
113+
; 32-DAG: [[m]]fhi $2
114+
; 32-DAG: [[m]]flo $3
115+
116+
; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6
117+
; DSP-DAG: mtlo $[[AC]], $7
118+
; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
119+
; DSP-DAG: mfhi $2, $[[AC]]
120+
; DSP-DAG: mflo $3, $[[AC]]
121+
122+
; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
123+
; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7
124+
; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
125+
; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $6
126+
; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
127+
; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
128+
129+
; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
130+
; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
131+
; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
132+
; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
133+
; 64-DAG: daddu $2, $[[T2]], $6
134+
135+
; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
136+
; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
137+
; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
138+
; 64R6-DAG: daddu $2, $[[T2]], $6
139+
31140
define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
32141
entry:
33142
%conv = sext i32 %a to i64
@@ -37,8 +146,41 @@ entry:
37146
ret i64 %add
38147
}
39148

40-
; 32: msub ${{[0-9]+}}
41-
; DSP: msub $ac
149+
; ALL-LABEL: msub1:
150+
151+
; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
152+
; 32-DAG: mtlo $6
153+
; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
154+
; 32-DAG: [[m]]fhi $2
155+
; 32-DAG: [[m]]flo $3
156+
157+
; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
158+
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
159+
; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
160+
; DSP-DAG: mfhi $2, $[[AC]]
161+
; DSP-DAG: mflo $3, $[[AC]]
162+
163+
; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
164+
; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
165+
; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
166+
; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]
167+
; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31
168+
; 32R6-DAG: subu $2, $[[T5]], $[[T4]]
169+
; 32R6-DAG: subu $3, $6, $[[T1]]
170+
171+
; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
172+
; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
173+
; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
174+
; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
175+
; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
176+
; 64-DAG: dsubu $2, $[[T3]], $[[T2]]
177+
178+
; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
179+
; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
180+
; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
181+
; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
182+
; 64R6-DAG: dsubu $2, $[[T3]], $[[T2]]
183+
42184
define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
43185
entry:
44186
%conv = sext i32 %c to i64
@@ -49,8 +191,48 @@ entry:
49191
ret i64 %sub
50192
}
51193

52-
; 32: msubu ${{[0-9]+}}
53-
; DSP: msubu $ac
194+
; ALL-LABEL: msub2:
195+
196+
; FIXME: We don't really need this instruction
197+
; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
198+
; 32-DAG: mtlo $6
199+
; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}}
200+
; 32-DAG: [[m]]fhi $2
201+
; 32-DAG: [[m]]flo $3
202+
203+
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
204+
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
205+
; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}}
206+
; DSP-DAG: mfhi $2, $[[AC]]
207+
; DSP-DAG: mflo $3, $[[AC]]
208+
209+
; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
210+
; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
211+
212+
; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
213+
; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
214+
; 32R6-DAG: negu $2, $[[T3]]
215+
; 32R6-DAG: subu $3, $6, $[[T1]]
216+
217+
; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
218+
; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
219+
; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
220+
; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
221+
; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
222+
; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
223+
; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
224+
; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
225+
; 64-DAG: dsubu $2, $[[T6]], $[[T4]]
226+
227+
; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
228+
; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
229+
; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
230+
; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
231+
; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
232+
; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
233+
; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
234+
; 64R6-DAG: dsubu $2, $[[T6]], $[[T4]]
235+
54236
define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
55237
entry:
56238
%conv = zext i32 %c to i64
@@ -61,8 +243,39 @@ entry:
61243
ret i64 %sub
62244
}
63245

64-
; 32: msub ${{[0-9]+}}
65-
; DSP: msub $ac
246+
; ALL-LABEL: msub3:
247+
248+
; FIXME: We don't really need this instruction
249+
; 32-DAG: mthi $6
250+
; 32-DAG: mtlo $7
251+
; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
252+
; 32-DAG: [[m]]fhi $2
253+
; 32-DAG: [[m]]flo $3
254+
255+
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
256+
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
257+
; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
258+
; DSP-DAG: mfhi $2, $[[AC]]
259+
; DSP-DAG: mflo $3, $[[AC]]
260+
261+
; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
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; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; 32R6-DAG: subu $2, $6, $[[T3]]
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; 32R6-DAG: subu $3, $7, $[[T1]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: dsubu $2, $6, $[[T2]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: dsubu $2, $6, $[[T2]]
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define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64

‎llvm/test/MC/Mips/mips32r6/invalid-mips32.s

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Original file line numberDiff line numberDiff line change
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# Instructions that are invalid
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#
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
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# RUN: 2>%t1
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# RUN: FileCheck %s < %t1
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.set noat
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madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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