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dsandersllvmdsandersllvm
committedMay 13, 2014
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
·
llvmorg-21-initllvmorg-3.5.0-rc1
1 parent ea3514e commit 387fc15

16 files changed

+125
-42
lines changed
 

‎llvm/lib/Target/Mips/MicroMipsInstrFPU.td

+4-4
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,9 @@ def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D,
7070
fsqrt>, ROUND_W_FM_MM<1, 0x28>;
7171

7272
def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
73-
ROUND_W_FM_MM<0, 0x4>;
73+
ROUND_W_FM_MM<0, 0x4>, INSN_MIPS3_32R2;
7474
def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
75-
ROUND_W_FM_MM<1, 0x4>;
75+
ROUND_W_FM_MM<1, 0x4>, INSN_MIPS3_32R2;
7676

7777
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
7878
ABS_FM_MM<0, 0xd>;
@@ -124,9 +124,9 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
124124
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
125125
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
126126
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
127-
MFC1_FM_MM<3>;
127+
MFC1_FM_MM<3>, ISA_MIPS32R2;
128128
def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
129-
MFC1_FM_MM<7>;
129+
MFC1_FM_MM<7>, ISA_MIPS32R2;
130130

131131
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
132132
MADDS_FM_MM<0x1>;

‎llvm/lib/Target/Mips/MicroMipsInstrInfo.td

+4-2
Original file line numberDiff line numberDiff line change
@@ -273,8 +273,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
273273
def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
274274
def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
275275
def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
276-
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>;
277-
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>;
276+
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
277+
ISA_MIPS32R2;
278+
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
279+
ISA_MIPS32R2;
278280

279281
/// Trap Instructions
280282
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;

‎llvm/lib/Target/Mips/Mips.td

+7-3
Original file line numberDiff line numberDiff line change
@@ -83,10 +83,14 @@ def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
8383
def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
8484
"Subset of MIPS-III that is also in MIPS32 "
8585
"[highly experimental]">;
86+
def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
87+
"Subset of MIPS-III that is also in MIPS32r2 "
88+
"[highly experimental]">;
8689
def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
8790
"MIPS III ISA Support [highly experimental]",
8891
[FeatureMips2, FeatureMips3_32,
89-
FeatureGP64Bit, FeatureFP64Bit]>;
92+
FeatureMips3_32r2, FeatureGP64Bit,
93+
FeatureFP64Bit]>;
9094
def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
9195
"Subset of MIPS-IV that is also in MIPS32 "
9296
"[highly experimental]">;
@@ -109,8 +113,8 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
109113
FeatureMips4_32]>;
110114
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
111115
"Mips32r2", "Mips32r2 ISA Support",
112-
[FeatureMips4_32r2, FeatureMips5_32r2,
113-
FeatureMips32]>;
116+
[FeatureMips3_32r2, FeatureMips4_32r2,
117+
FeatureMips5_32r2, FeatureMips32]>;
114118
def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
115119
"Mips32r6",
116120
"Mips32r6 ISA Support [experimental]",

‎llvm/lib/Target/Mips/MipsInstrFPU.td

+4-4
Original file line numberDiff line numberDiff line change
@@ -298,9 +298,9 @@ let DecoderNamespace = "Mips64" in {
298298
def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
299299
ABSS_FM<0x20, 20>;
300300
def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
301-
ABSS_FM<0x25, 16>, INSN_MIPS3_32;
301+
ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
302302
def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
303-
ABSS_FM<0x25, 17>, INSN_MIPS3_32;
303+
ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
304304

305305
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
306306
ABSS_FM<0x20, 17>, FGR_32;
@@ -354,9 +354,9 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
354354
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
355355
bitconvert>, MFC1_FM<4>;
356356
def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
357-
MFC1_FM<3>;
357+
MFC1_FM<3>, ISA_MIPS32R2;
358358
def MTHC1 : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
359-
MFC1_FM<7>;
359+
MFC1_FM<7>, ISA_MIPS32R2;
360360
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
361361
bitconvert>, MFC1_FM<1>, ISA_MIPS3;
362362
def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,

‎llvm/lib/Target/Mips/MipsInstrInfo.td

+7-2
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,8 @@ def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150150
AssemblerPredicate<"FeatureMips2">;
151151
def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152152
AssemblerPredicate<"FeatureMips3_32">;
153+
def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154+
AssemblerPredicate<"FeatureMips3_32r2">;
153155
def HasMips3 : Predicate<"Subtarget.hasMips3()">,
154156
AssemblerPredicate<"FeatureMips3">;
155157
def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
@@ -221,6 +223,9 @@ class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
221223
// The portions of MIPS-III that were also added to MIPS32
222224
class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
223225

226+
// The portions of MIPS-III that were also added to MIPS32
227+
class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
228+
224229
// The portions of MIPS-IV that were also added to MIPS32
225230
class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
226231

@@ -1084,8 +1089,8 @@ def TRAP : TrapBase<BREAK>;
10841089
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
10851090
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
10861091

1087-
def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1088-
def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1092+
def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1093+
def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
10891094

10901095
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
10911096
AdditionalPredicates = [NotInMicroMips] in {

‎llvm/lib/Target/Mips/MipsSubtarget.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,12 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
8080
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
8181
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
8282
IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
83-
HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false),
84-
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
85-
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
86-
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
87-
HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
88-
TargetTriple(TT) {
83+
HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
84+
HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
85+
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
86+
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
87+
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
88+
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
8989
std::string CPUName = CPU;
9090
CPUName = selectMipsCPU(TT, CPUName);
9191

‎llvm/lib/Target/Mips/MipsSubtarget.h

+3
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
8282
// HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
8383
bool HasMips3_32;
8484

85+
// HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
86+
bool HasMips3_32r2;
87+
8588
// HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
8689
bool HasMips4_32;
8790

‎llvm/test/MC/Mips/micromips-control-instructions.s

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
1+
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \
22
# RUN: | FileCheck -check-prefix=CHECK-EL %s
3-
# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
3+
# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \
44
# RUN: | FileCheck -check-prefix=CHECK-EB %s
55
# Check that the assembler can handle the documented syntax
66
# for control instructions.

‎llvm/test/MC/Mips/mips2/invalid-mips32r2-xfail.s

+11
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
# Instructions that are supposed to be invalid but currently aren't
2+
# This test will XPASS if any insn stops assembling.
3+
#
4+
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
5+
# RUN: 2> %t1
6+
# RUN: not FileCheck %s < %t1
7+
# XFAIL: *
8+
9+
# CHECK-NOT: error
10+
.set noat
11+
rdhwr $sp,$11

‎llvm/test/MC/Mips/mips2/invalid-mips32r2.s

+59
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
# Instructions that are invalid
2+
#
3+
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \
4+
# RUN: 2>%t1
5+
# RUN: FileCheck %s < %t1
6+
7+
.set noat
8+
clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9+
clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10+
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11+
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12+
deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13+
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14+
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15+
eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16+
ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17+
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18+
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19+
madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20+
madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21+
madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22+
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23+
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24+
maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25+
mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26+
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27+
movf $gp,$t0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28+
movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29+
movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30+
movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31+
movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32+
movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33+
movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34+
movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35+
movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36+
movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
37+
movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38+
movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39+
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40+
msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41+
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42+
msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43+
mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44+
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
45+
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46+
nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47+
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48+
nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49+
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
50+
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
51+
rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
52+
rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53+
rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
54+
sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55+
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56+
seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57+
suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
58+
swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59+
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

‎llvm/test/MC/Mips/mips32/invalid-mips32r2-xfail.s

-6
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,4 @@
88

99
# CHECK-NOT: error
1010
.set noat
11-
cvt.l.d $f24,$f15
12-
cvt.l.s $f11,$f29
13-
di $s8
14-
ei $t6
15-
mfhc1 $s8,$f24
16-
mthc1 $zero,$f16
1711
rdhwr $sp,$11

‎llvm/test/MC/Mips/mips32/invalid-mips32r2.s

+8-2
Original file line numberDiff line numberDiff line change
@@ -4,21 +4,27 @@
44
# RUN: 2>%t1
55
# RUN: FileCheck %s < %t1
66

7-
.set noat
7+
.set noat
8+
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9+
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10+
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11+
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
812
ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
913
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1014
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1115
madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1216
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17+
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1318
msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1419
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20+
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1521
nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1622
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1723
nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1824
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1925
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20-
rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2126
rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27+
rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2228
rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2329
sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2430
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

‎llvm/test/MC/Mips/mips4/invalid-mips64r2-xfail.s

-4
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,4 @@
88

99
# CHECK-NOT: error
1010
.set noat
11-
di $s8
12-
ei $t6
13-
mfhc1 $s8,$f24
14-
mthc1 $zero,$f16
1511
rdhwr $sp,$11

‎llvm/test/MC/Mips/mips4/invalid-mips64r2.s

+4-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
# Instructions that are invalid
22
#
3-
# FIXME: This test should be moved to the mips5 directory when mips5 is supported
43
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
54
# RUN: 2>%t1
65
# RUN: FileCheck %s < %t1
@@ -11,19 +10,23 @@
1110
dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1211
dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1312
deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13+
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1414
dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1515
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16+
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1617
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1718
madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1819
madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1920
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2021
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2122
maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2223
mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24+
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2325
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2426
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2527
msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2628
mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29+
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2730
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2831
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
2932
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

‎llvm/test/MC/Mips/mips64/invalid-mips64r2-xfail.s

-4
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,4 @@
88

99
# CHECK-NOT: error
1010
.set noat
11-
di $s8
12-
ei $t6
13-
mfhc1 $s8,$f24
14-
mthc1 $zero,$f16
1511
rdhwr $sp,$11

‎llvm/test/MC/Mips/mips64/invalid-mips64r2.s

+6-2
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,19 @@
55
# RUN: FileCheck %s < %t1
66

77
.set noat
8-
drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8+
di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
99
drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10-
drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10+
drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1111
drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12+
drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1213
drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1314
dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1415
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16+
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1517
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18+
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1619
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20+
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1721
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1822
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1923
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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