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dsandersllvmdsandersllvm
committedMay 12, 2014
[mips] Fold FeatureSEInReg into FeatureMips32r2
Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
·
llvmorg-21-initllvmorg-3.5.0-rc1
1 parent 39d0051 commit fcea810

7 files changed

+20
-26
lines changed
 

‎llvm/lib/Target/Mips/MicroMipsInstrInfo.td

+4-2
Original file line numberDiff line numberDiff line change
@@ -222,8 +222,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
222222
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
223223

224224
/// Sign Ext In Register Instructions.
225-
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM_MM<0x0ac>;
226-
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>;
225+
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
226+
SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
227+
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
228+
SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
227229

228230
/// Word Swap Bytes Within Halfwords
229231
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,

‎llvm/lib/Target/Mips/Mips.td

+1-4
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,6 @@ def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
7575
"Enable eabi ABI">;
7676
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
7777
"true", "Enable vector FPU instructions.">;
78-
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
79-
"Enable 'signext in register' instructions.">;
8078
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
8179
"Enable 'count leading bits' instructions.">;
8280
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
@@ -110,8 +108,7 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
110108
FeatureMips4_32, FeatureBitCount]>;
111109
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
112110
"Mips32r2", "Mips32r2 ISA Support",
113-
[FeatureMips4_32r2, FeatureMips32,
114-
FeatureSEInReg]>;
111+
[FeatureMips4_32r2, FeatureMips32]>;
115112
def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
116113
"Mips32r6",
117114
"Mips32r6 ISA Support [experimental]",

‎llvm/lib/Target/Mips/Mips64InstrInfo.td

+4-2
Original file line numberDiff line numberDiff line change
@@ -209,8 +209,10 @@ def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
209209
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
210210

211211
/// Sign Ext In Register Instructions.
212-
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
213-
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
212+
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
213+
ISA_MIPS32R2;
214+
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
215+
ISA_MIPS32R2;
214216
}
215217

216218
/// Count Leading

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -352,7 +352,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
352352

353353
setInsertFencesForAtomic(true);
354354

355-
if (!Subtarget->hasSEInReg()) {
355+
if (!Subtarget->hasMips32r2()) {
356356
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
357357
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
358358
}

‎llvm/lib/Target/Mips/MipsInstrInfo.td

+5-8
Original file line numberDiff line numberDiff line change
@@ -146,8 +146,6 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
146146
//===----------------------------------------------------------------------===//
147147
// Mips Instruction Predicate Definitions.
148148
//===----------------------------------------------------------------------===//
149-
def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150-
AssemblerPredicate<"FeatureSEInReg">;
151149
def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152150
AssemblerPredicate<"FeatureBitCount">;
153151
def HasMips2 : Predicate<"Subtarget.hasMips2()">,
@@ -224,8 +222,6 @@ class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
224222
// The portions of MIPS-IV that were also added to MIPS32R2
225223
class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
226224

227-
class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
228-
229225
//===----------------------------------------------------------------------===//
230226

231227
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
@@ -839,8 +835,7 @@ class CountLeading1<string opstr, RegisterOperand RO>:
839835
class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
840836
InstrItinClass itin> :
841837
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
842-
[(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>,
843-
INSN_SEINREG;
838+
[(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
844839

845840
// Subword Swap
846841
class SubwordSwap<string opstr, RegisterOperand RO>:
@@ -1165,8 +1160,10 @@ def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
11651160
}
11661161

11671162
/// Sign Ext In Register Instructions.
1168-
def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1169-
def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1163+
def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1164+
SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1165+
def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1166+
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
11701167

11711168
/// Count Leading
11721169
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;

‎llvm/lib/Target/Mips/MipsSubtarget.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -81,11 +81,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
8181
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
8282
IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
8383
HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false),
84-
HasMips4_32r2(false), HasSEInReg(false), HasBitCount(false),
85-
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
86-
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
87-
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
88-
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
84+
HasMips4_32r2(false), HasBitCount(false), InMips16Mode(false),
85+
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
86+
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
87+
HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
88+
TargetTriple(TT) {
8989
std::string CPUName = CPU;
9090
CPUName = selectMipsCPU(TT, CPUName);
9191

‎llvm/lib/Target/Mips/MipsSubtarget.h

-4
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
8888
// HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
8989
bool HasMips4_32r2;
9090

91-
// HasSEInReg - SEB and SEH (signext in register) instructions.
92-
bool HasSEInReg;
93-
9491
// HasBitCount - Count leading '1' and '0' bits.
9592
bool HasBitCount;
9693

@@ -211,7 +208,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
211208
}
212209

213210
/// Features related to the presence of specific instructions.
214-
bool hasSEInReg() const { return HasSEInReg; }
215211
bool hasBitCount() const { return HasBitCount; }
216212
bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
217213

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