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author
Reed Kotler
committedMay 1, 2014
Add basic functionality for assignment of ints.
This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel Test Plan: simplestore.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3527 llvm-svn: 207790
·
llvmorg-21-initllvmorg-3.5.0-rc1
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‎llvm/lib/Target/Mips/MipsFastISel.cpp

+167-1
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,12 @@
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/FastISel.h"
6-
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLibraryInfo.h"
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#include "MipsRegisterInfo.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
@@ -15,6 +17,21 @@ using namespace llvm;
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namespace {
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// All possible address modes.
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typedef struct Address {
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enum { RegBase, FrameIndexBase } BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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// Innocuous defaults for our address.
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Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
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} Address;
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1835
class MipsFastISel final : public FastISel {
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
@@ -46,10 +63,120 @@ class MipsFastISel final : public FastISel {
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}
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bool TargetSelectInstruction(const Instruction *I) override;
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unsigned TargetMaterializeConstant(const Constant *C) override;
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bool ComputeAddress(const Value *Obj, Address &Addr);
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private:
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bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool SelectRet(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
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unsigned MaterializeInt(const Constant *C, MVT VT);
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};
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bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (evt == MVT::Other || !evt.isSimple())
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return false;
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VT = evt.getSimpleVT();
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// Handle all legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// We will extend this in a later patch:
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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return false;
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}
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bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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//
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if (isa<Instruction>(Obj))
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return false;
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else if (isa<ConstantExpr>(Obj))
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return false;
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Addr.Base.Reg = getRegForValue(Obj);
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return Addr.Base.Reg != 0;
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}
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// Materialize a constant into a register, and return the register
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// number (or zero if we failed to handle it).
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unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return MaterializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return MaterializeInt(C, VT);
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return 0;
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}
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bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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//
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if (VT != MVT::i32)
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return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::SW))
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.addReg(SrcReg)
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.addReg(Addr.Base.Reg)
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.addImm(Addr.Offset);
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return true;
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}
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bool MipsFastISel::SelectStore(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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unsigned SrcReg = 0;
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// Atomic stores need special handling.
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if (cast<StoreInst>(I)->isAtomic())
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return false;
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// Verify we have a legal type before going any further.
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MVT VT;
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if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
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return false;
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// Get the value to be stored into a register.
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SrcReg = getRegForValue(Op0);
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if (SrcReg == 0)
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return false;
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(1), Addr))
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return false;
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if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
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return false;
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return true;
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}
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bool MipsFastISel::SelectRet(const Instruction *I) {
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const ReturnInst *Ret = cast<ReturnInst>(I);
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@@ -69,13 +196,52 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
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switch (I->getOpcode()) {
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default:
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break;
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case Instruction::Store:
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return SelectStore(I);
72201
case Instruction::Ret:
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return SelectRet(I);
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}
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return false;
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}
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}
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unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
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return 0;
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}
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unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
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// For now 32-bit only.
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if (VT != MVT::i32)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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unsigned DestReg = createResultReg(RC);
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const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
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bool IsThreadLocal = GVar && GVar->isThreadLocal();
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// TLS not supported at this time.
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if (IsThreadLocal)
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return 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LW), DestReg)
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.addReg(MFI->getGlobalBaseReg())
225+
.addGlobalAddress(GV, 0, MipsII::MO_GOT);
226+
return DestReg;
227+
}
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unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
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if (VT != MVT::i32)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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// If the constant is in range, use a load-immediate.
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const ConstantInt *CI = cast<ConstantInt>(C);
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if (isInt<16>(CI->getSExtValue())) {
235+
unsigned Opc = Mips::ADDiu;
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unsigned ImmReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
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.addReg(Mips::ZERO)
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.addImm(CI->getSExtValue());
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return ImmReg;
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}
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return 0;
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}
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79245
namespace llvm {
80246
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
81247
const TargetLibraryInfo *libInfo) {

‎llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll

+15
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@@ -0,0 +1,15 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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@abcd = external global i32
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; Function Attrs: nounwind
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define void @foo() {
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entry:
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store i32 12345, i32* @abcd, align 4
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; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345
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; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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