Encode native floating point types in data layout string.

[dirty]

Summary

Add support for explicitly encoding native floating point types in the data layout string.

[jholewinski]

NVPTX changes look reasonable to me.

include/llvm/IR/DataLayout.h

private:
   bool BigEndian;
 
   unsigned StackNaturalAlign;
 
   enum ManglingModeT { MM_None, MM_ELF, MM_MachO, MM_WINCOFF, MM_Mips };
   ManglingModeT ManglingMode;
 
   SmallVector<unsigned char, 8> LegalIntWidths;
+  SmallVector<unsigned char, 8> LegalFloatWidths; ///< Legal Floats.
 
   /// \brief Primitive type alignment data.
   SmallVector<LayoutAlignElem, 16> Alignments;
 
   typedef SmallVector<PointerAlignElem, 8> PointersTy;
   PointersTy Pointers;
 
   PointersTy::const_iterator
public:
   DataLayout(const DataLayout &DL) : LayoutMap(nullptr) { *this = DL; }
 
   DataLayout &operator=(const DataLayout &DL) {
     clear();
     BigEndian = DL.isBigEndian();
     StackNaturalAlign = DL.StackNaturalAlign;
     ManglingMode = DL.ManglingMode;
     LegalIntWidths = DL.LegalIntWidths;
+    LegalFloatWidths = DL.LegalFloatWidths,
     Alignments = DL.Alignments;
     Pointers = DL.Pointers;
     return *this;
   }
 
   bool operator==(const DataLayout &Other) const;
   bool operator!=(const DataLayout &Other) const { return !(*this == Other); }
 
bool isLegalInteger(unsigned Width) const {
     for (unsigned LegalIntWidth : LegalIntWidths)
       if (LegalIntWidth == Width)
         return true;
     return false;
   }
 
   bool isIllegalInteger(unsigned Width) const { return !isLegalInteger(Width); }
 
+  /// isLegalFloat - This function returns true if the specified type is
+  /// known to be a native float type supported by the CPU.  For example,
+  /// f32 is not native on most ARM Thumb CPUs and f37 is not native on any known
+  /// one.  This returns false if the float width is not legal.
+  ///
+  /// The width is specified in bits.
+  ///
+  bool isLegalFloat(unsigned Width) const {
+    for (unsigned i = 0, e = LegalFloatWidths.size(); i != e; ++i)
+      if (LegalFloatWidths[i] == Width)
+        return true;
+    return false;
+  }
+
+  bool isIllegalFloat(unsigned Width) const {
+    return !isLegalFloat(Width);
+  }
+
   /// Returns true if the given alignment exceeds the natural stack alignment.
   bool exceedsNaturalStackAlignment(unsigned Align) const {
     return (StackNaturalAlign != 0) && (Align > StackNaturalAlign);
   }
 
   unsigned getStackAlignment() const { return StackNaturalAlign; }
 
   bool hasMicrosoftFastStdCallMangling() const {

lib/IR/DataLayout.cpp

case 'a': {
         Split = split(Rest, ':');
         PrefAlign = inBytes(getInt(Tok));
       }
 
       setAlignment(AlignType, ABIAlign, PrefAlign, Size);
 
       break;
     }
-    case 'n':  // Native integer types.
+    case 'n':  // Native integer and float types.
       for (;;) {
+      if (Tok.front() == 'f') {
+        unsigned Width = getInt(Tok.drop_front());
+              if (Width == 0)
+                report_fatal_error(
+                    "Zero width native float type in datalayout string");
+        LegalFloatWidths.push_back(Width);
+      } else {
+        if (Tok.front() == 'i')
+          Tok = Tok.drop_front();
               unsigned Width = getInt(Tok);
               if (Width == 0)
                 report_fatal_error(
                     "Zero width native integer type in datalayout string");
               LegalIntWidths.push_back(Width);
+      }
         if (Rest.empty())
           break;
         Split = split(Rest, ':');
       }
       break;
     case 'S': { // Stack natural alignment.
       StackNaturalAlign = inBytes(getInt(Tok));
       break;

lib/Target/AArch64/AArch64Subtarget.cpp

: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
       HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
       HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), CPUString(CPU),
       TargetTriple(TT),
       // This nested ternary is horrible, but DL needs to be properly
       // initialized
       // before TLInfo is constructed.
       DL(isTargetMachO()
              ? "e-m:o-i64:64-i128:128-n32:64-S128"
-             : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
-                             : "E-m:e-i64:64-i128:128-n32:64-S128")),
+             : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128-nf32:f64"
+                             : "E-m:e-i64:64-i128:128-n32:64-S128-nf32:f64")),
       FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)),
       TSInfo(&DL), TLInfo(TM) {}
 
 /// ClassifyGlobalReference - Find the target operand flags that describe
 /// how a global value should be referenced for the current subtarget.
 unsigned char
 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
                                         const TargetMachine &TM) const {

lib/Target/ARM/ARMSubtarget.h

public:
   bool hasVFP3() const { return HasVFPv3; }
   bool hasVFP4() const { return HasVFPv4; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON;  }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
   bool hasVirtualization() const { return HasVirtualization; }
   bool useNEONForSinglePrecisionFP() const {
-    return hasNEON() && UseNEONForSinglePrecisionFP; }
+    return hasNEON() && UseNEONForSinglePrecisionFP;
+  }
+  bool hasFloatingPoint() const { return HasVFPv2 || HasVFPv3 || HasVFPv4 || HasFPARMv8 || HasNEON; }
 
   bool hasDivide() const { return HasHardwareDivide; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
   bool hasT2ExtractPack() const { return HasT2ExtractPack; }
   bool hasDataBarrier() const { return HasDataBarrier; }
   bool hasAnyDataBarrier() const {
     return HasDataBarrier || (hasV6Ops() && !isThumb());
   }

lib/Target/ARM/ARMSubtarget.cpp

static std::string computeDataLayout(ARMSubtarget &ST) {
   // aligned everywhere else.
   if (ST.isTargetNaCl())
     Ret += "-S128";
   else if (ST.isAAPCS_ABI())
     Ret += "-S64";
   else
     Ret += "-S32";
 
+  if (ST.hasFloatingPoint()) {
+    if (ST.hasFP16())
+      Ret += "-nf16";
+    else if (ST.useNEONForSinglePrecisionFP())
+      Ret += "-nf32";
+    else
+      Ret += "-nf32:f64";
+  }
+
   return Ret;
 }
 
 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
 /// so that we can use initializer lists for subtarget initialization.
 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();

lib/Target/Hexagon/HexagonSubtarget.cpp

cl::desc(
       "Do not generate V4 MEMOP in code generation for Hexagon target"));
 
 static cl::opt<bool>
 EnableIEEERndNear(
     "enable-hexagon-ieee-rnd-near",
     cl::Hidden, cl::ZeroOrMore, cl::init(false),
     cl::desc("Generate non-chopped conversion from fp to int."));
 
+static std::string computeDataLayout(const HexagonSubtarget &ST) {
+  std::string Ret = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
+
+  // Add floating point.
+  if (ST.hasV5TOps())
+    Ret += "-nf32";
+
+  return Ret;
+}
+
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   // If the programmer has not specified a Hexagon version, default to -mv4.
   if (CPUString.empty())
     CPUString = "hexagonv4";
 
   if (CPUString == "hexagonv2") {
     HexagonArchVersion = V2;
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
 
   ParseSubtargetFeatures(CPUString, FS);
   return *this;
 }
 
 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
                                    const TargetMachine &TM)
     : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
-      DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"),
-      InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
+      DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
+      InstrInfo(*this), TLInfo(TM),
       TSInfo(DL), FrameLowering() {
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
   // UseMemOps on by default unless disabled explicitly
   if (DisableMemOps)
     UseMemOps = false;

lib/Target/Mips/MipsSubtarget.cpp

static std::string computeDataLayout(const MipsSubtarget &ST) {
   // 32 bit registers are always available and the stack is at least 64 bit
   // aligned. On N64 64 bit registers are also available and the stack is
   // 128 bit aligned.
   if (ST.isABI_N64() || ST.isABI_N32())
     Ret += "-n32:64-S128";
   else
     Ret += "-n32-S64";
 
+  // 32 and 64 bit floating points are valid.
+  Ret += "-nf32:f64";
+
   return Ret;
 }
 
 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
                              const std::string &FS, bool little,
                              const MipsTargetMachine *_TM)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),

lib/Target/NVPTX/NVPTXSubtarget.cpp

 #define GET_SUBTARGETINFO_ENUM
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "NVPTXGenSubtargetInfo.inc"
 
 // Pin the vtable to this file.
 void NVPTXSubtarget::anchor() {}
 
-static std::string computeDataLayout(bool is64Bit) {
+static std::string computeDataLayout(const NVPTXSubtarget &ST) {
   std::string Ret = "e";
 
-  if (!is64Bit)
+  if (!ST.is64Bit())
     Ret += "-p:32:32";
 
   Ret += "-i64:64-v16:16-v32:32-n16:32:64";
 
+  // Add floating point.
+  Ret += "-nf32";
+
+  if (ST.hasDouble())
+    Ret += ":f64";
+
   return Ret;
 }
 
 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
     // Provide the default CPU if we don't have one.
   if (CPU.empty() && FS.size())
     llvm_unreachable("we are not using FeatureStr");
   TargetName = CPU.empty() ? "sm_20" : CPU;
 
   ParseSubtargetFeatures(TargetName, FS);
 
   // Set default to PTX 3.2 (CUDA 5.5)
   if (PTXVersion == 0) {
     PTXVersion = 32;
   }
 
   return *this;
 }
 
 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM,
                                bool is64Bit)
     : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
-      SmVersion(20), DL(computeDataLayout(is64Bit)),
-      InstrInfo(initializeSubtargetDependencies(CPU, FS)),
+      SmVersion(20), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
+      InstrInfo(*this),
       TLInfo((const NVPTXTargetMachine &)TM), TSInfo(&DL),
       FrameLowering(*this) {
 
   Triple T(TT);
 
   if (T.getOS() == Triple::NVCL)
     drvInterface = NVPTX::NVCL;
   else
     drvInterface = NVPTX::CUDA;
 }

lib/Target/PowerPC/PPCSubtarget.cpp

else
     Ret += "-f64:32:64";
 
   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
   if (is64Bit)
     Ret += "-n32:64";
   else
     Ret += "-n32";
 
+  Ret += "-nf32:f64";
+
+  // PPC64 has support for 128-bit floating point (long double)
+  if (is64Bit)
+    Ret += ":f128";
+
   return Ret;
 }
 
 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;

lib/Target/R600/AMDGPUSubtarget.cpp

static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
   if (ST.is64bit()) {
     // 32-bit private, local, and region pointers. 64-bit global and constant.
     Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
   }
 
   Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
          "-v512:512-v1024:1024-v2048:2048-n32:64";
 
+  // Add floating point.
+  Ret += "-nf32";
+
+  if (ST.hasHWFP64())
+    Ret += ":f64";
   return Ret;
 }
 
 AMDGPUSubtarget &
 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef GPU, StringRef FS) {
   // Determine default and user-specified characteristics
   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
   // enabled, but some instructions do not respect them and they run at the

lib/Target/Sparc/SparcSubtarget.cpp

static std::string computeDataLayout(const SparcSubtarget &ST) {
   else
     Ret += "-f128:64-n32";
 
   if (ST.is64Bit())
     Ret += "-S128";
   else
     Ret += "-S64";
 
+  // 32 and 64 bit floating points are valid.
+  Ret += "-nf32:f64";
+
   return Ret;
 }
 
 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
   IsV9 = false;
   V8DeprecatedInsts = false;
   IsVIS = false;

lib/Target/SystemZ/SystemZSubtarget.cpp

SystemZSubtarget::SystemZSubtarget(const std::string &TT,
                                    const TargetMachine &TM)
     : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasFastSerialization(false), HasInterlockedAccess1(false),
       TargetTriple(TT),
       // Make sure that global data has at least 16 bits of alignment by
       // default, so that we can refer to it using LARL.  We don't have any
       // special requirements for stack variables though.
-      DL("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"),
+      DL("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64-nf32:f64"),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
       TSInfo(DL), FrameLowering() {}
 
 // Return true if GV binds locally under reloc model RM.
 static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) {
   // For non-PIC, all symbols bind locally.
   if (RM == Reloc::Static)
     return true;

lib/Target/X86/X86Subtarget.cpp

else
     Ret += "-n8:16:32";
 
   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
   if (!TT.isArch64Bit() && TT.isOSWindows())
     Ret += "-S32";
   else
     Ret += "-S128";
 
+  // 32, 64, and 80 bit floating points are valid.
+  Ret += "-nf32:f64:f80";
+
   return Ret;
 }
 
 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
                                                             StringRef FS) {
   initializeEnvironment();
   initSubtargetFeatures(CPU, FS);
   return *this;