@@ -32,6 +32,12 @@ let Namespace = "AArch64" in {
3232 def qsub : SubRegIndex<64>;
3333 def sube64 : SubRegIndex<64>;
3434 def subo64 : SubRegIndex<64>;
35+ // SVE
36+ def zsub : SubRegIndex<128>;
37+ // Note: zsub_hi should never be used directly because it represents
38+ // the scalable part of the SVE vector and cannot be manipulated as a
39+ // subvector in the same way the lower 128bits can.
40+ def zsub_hi : SubRegIndex<128>;
3541 // Note: Code depends on these having consecutive numbers
3642 def dsub0 : SubRegIndex<64>;
3743 def dsub1 : SubRegIndex<64>;
@@ -645,3 +651,119 @@ def XSeqPairClassOperand :
645651
646652
647653//===----- END: v8.1a atomic CASP register operands -----------------------===//
654+
655+ // The part of SVE registers that don't overlap Neon registers.
656+ // These are only used as part of clobber lists.
657+ def Z0_HI : AArch64Reg<0, "z0_hi">;
658+ def Z1_HI : AArch64Reg<1, "z1_hi">;
659+ def Z2_HI : AArch64Reg<2, "z2_hi">;
660+ def Z3_HI : AArch64Reg<3, "z3_hi">;
661+ def Z4_HI : AArch64Reg<4, "z4_hi">;
662+ def Z5_HI : AArch64Reg<5, "z5_hi">;
663+ def Z6_HI : AArch64Reg<6, "z6_hi">;
664+ def Z7_HI : AArch64Reg<7, "z7_hi">;
665+ def Z8_HI : AArch64Reg<8, "z8_hi">;
666+ def Z9_HI : AArch64Reg<9, "z9_hi">;
667+ def Z10_HI : AArch64Reg<10, "z10_hi">;
668+ def Z11_HI : AArch64Reg<11, "z11_hi">;
669+ def Z12_HI : AArch64Reg<12, "z12_hi">;
670+ def Z13_HI : AArch64Reg<13, "z13_hi">;
671+ def Z14_HI : AArch64Reg<14, "z14_hi">;
672+ def Z15_HI : AArch64Reg<15, "z15_hi">;
673+ def Z16_HI : AArch64Reg<16, "z16_hi">;
674+ def Z17_HI : AArch64Reg<17, "z17_hi">;
675+ def Z18_HI : AArch64Reg<18, "z18_hi">;
676+ def Z19_HI : AArch64Reg<19, "z19_hi">;
677+ def Z20_HI : AArch64Reg<20, "z20_hi">;
678+ def Z21_HI : AArch64Reg<21, "z21_hi">;
679+ def Z22_HI : AArch64Reg<22, "z22_hi">;
680+ def Z23_HI : AArch64Reg<23, "z23_hi">;
681+ def Z24_HI : AArch64Reg<24, "z24_hi">;
682+ def Z25_HI : AArch64Reg<25, "z25_hi">;
683+ def Z26_HI : AArch64Reg<26, "z26_hi">;
684+ def Z27_HI : AArch64Reg<27, "z27_hi">;
685+ def Z28_HI : AArch64Reg<28, "z28_hi">;
686+ def Z29_HI : AArch64Reg<29, "z29_hi">;
687+ def Z30_HI : AArch64Reg<30, "z30_hi">;
688+ def Z31_HI : AArch64Reg<31, "z31_hi">;
689+
690+ // SVE variable-size vector registers
691+ let SubRegIndices = [zsub,zsub_hi] in {
692+ def Z0 : AArch64Reg<0, "z0", [Q0, Z0_HI]>, DwarfRegNum<[96]>;
693+ def Z1 : AArch64Reg<1, "z1", [Q1, Z1_HI]>, DwarfRegNum<[97]>;
694+ def Z2 : AArch64Reg<2, "z2", [Q2, Z2_HI]>, DwarfRegNum<[98]>;
695+ def Z3 : AArch64Reg<3, "z3", [Q3, Z3_HI]>, DwarfRegNum<[99]>;
696+ def Z4 : AArch64Reg<4, "z4", [Q4, Z4_HI]>, DwarfRegNum<[100]>;
697+ def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>;
698+ def Z6 : AArch64Reg<6, "z6", [Q6, Z6_HI]>, DwarfRegNum<[102]>;
699+ def Z7 : AArch64Reg<7, "z7", [Q7, Z7_HI]>, DwarfRegNum<[103]>;
700+ def Z8 : AArch64Reg<8, "z8", [Q8, Z8_HI]>, DwarfRegNum<[104]>;
701+ def Z9 : AArch64Reg<9, "z9", [Q9, Z9_HI]>, DwarfRegNum<[105]>;
702+ def Z10 : AArch64Reg<10, "z10", [Q10, Z10_HI]>, DwarfRegNum<[106]>;
703+ def Z11 : AArch64Reg<11, "z11", [Q11, Z11_HI]>, DwarfRegNum<[107]>;
704+ def Z12 : AArch64Reg<12, "z12", [Q12, Z12_HI]>, DwarfRegNum<[108]>;
705+ def Z13 : AArch64Reg<13, "z13", [Q13, Z13_HI]>, DwarfRegNum<[109]>;
706+ def Z14 : AArch64Reg<14, "z14", [Q14, Z14_HI]>, DwarfRegNum<[110]>;
707+ def Z15 : AArch64Reg<15, "z15", [Q15, Z15_HI]>, DwarfRegNum<[111]>;
708+ def Z16 : AArch64Reg<16, "z16", [Q16, Z16_HI]>, DwarfRegNum<[112]>;
709+ def Z17 : AArch64Reg<17, "z17", [Q17, Z17_HI]>, DwarfRegNum<[113]>;
710+ def Z18 : AArch64Reg<18, "z18", [Q18, Z18_HI]>, DwarfRegNum<[114]>;
711+ def Z19 : AArch64Reg<19, "z19", [Q19, Z19_HI]>, DwarfRegNum<[115]>;
712+ def Z20 : AArch64Reg<20, "z20", [Q20, Z20_HI]>, DwarfRegNum<[116]>;
713+ def Z21 : AArch64Reg<21, "z21", [Q21, Z21_HI]>, DwarfRegNum<[117]>;
714+ def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
715+ def Z23 : AArch64Reg<23, "z23", [Q23, Z23_HI]>, DwarfRegNum<[119]>;
716+ def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
717+ def Z25 : AArch64Reg<25, "z25", [Q25, Z25_HI]>, DwarfRegNum<[121]>;
718+ def Z26 : AArch64Reg<26, "z26", [Q26, Z26_HI]>, DwarfRegNum<[122]>;
719+ def Z27 : AArch64Reg<27, "z27", [Q27, Z27_HI]>, DwarfRegNum<[123]>;
720+ def Z28 : AArch64Reg<28, "z28", [Q28, Z28_HI]>, DwarfRegNum<[124]>;
721+ def Z29 : AArch64Reg<29, "z29", [Q29, Z29_HI]>, DwarfRegNum<[125]>;
722+ def Z30 : AArch64Reg<30, "z30", [Q30, Z30_HI]>, DwarfRegNum<[126]>;
723+ def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
724+ }
725+
726+ class SVERegOp <string Suffix, AsmOperandClass C,
727+ RegisterClass RC> : RegisterOperand<RC> {
728+ let PrintMethod = !if(!eq(Suffix, ""),
729+ "printSVERegOp<>",
730+ "printSVERegOp<'" # Suffix # "'>");
731+ let ParserMatchClass = C;
732+ }
733+
734+ class ZPRRegOp <string Suffix, AsmOperandClass C,
735+ RegisterClass RC> : SVERegOp<Suffix, C, RC> {}
736+
737+ //******************************************************************************
738+
739+ // SVE vector register class
740+ def ZPR : RegisterClass<"AArch64",
741+ [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
742+ nxv2f16, nxv4f16, nxv8f16,
743+ nxv1f32, nxv2f32, nxv4f32,
744+ nxv1f64, nxv2f64],
745+ 128, (sequence "Z%u", 0, 31)> {
746+ let Size = 128;
747+ }
748+
749+ class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
750+ let Name = "SVE" # name # "Reg";
751+ let PredicateMethod = "isSVEDataVectorRegOfWidth<" # Width # ">";
752+ let RenderMethod = "addRegOperands";
753+ let ParserMethod = "tryParseSVEDataVector<"
754+ # !if(!eq(Width, -1), "false", "true") # ">";
755+ }
756+
757+ def ZPRAsmOpAny : ZPRAsmOperand<"VectorAny", -1>;
758+ def ZPRAsmOp8 : ZPRAsmOperand<"VectorB", 8>;
759+ def ZPRAsmOp16 : ZPRAsmOperand<"VectorH", 16>;
760+ def ZPRAsmOp32 : ZPRAsmOperand<"VectorS", 32>;
761+ def ZPRAsmOp64 : ZPRAsmOperand<"VectorD", 64>;
762+ def ZPRAsmOp128 : ZPRAsmOperand<"VectorQ", 128>;
763+
764+ def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ZPR>;
765+ def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ZPR>;
766+ def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ZPR>;
767+ def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ZPR>;
768+ def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ZPR>;
769+ def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ZPR>;
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