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Commit 5577297

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author
Krzysztof Parzyszek
committedSep 15, 2017
[Hexagon] Switch to parameterized register classes for HVX
This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
1 parent 3580ef1 commit 5577297

29 files changed

+2593
-13971
lines changed
 

‎llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

+19-19
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
106106
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
107107
uint64_t Address,
108108
const void *Decoder);
109-
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
109+
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
110110
uint64_t Address,
111111
const void *Decoder);
112112
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -115,13 +115,13 @@ static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
115115
static DecodeStatus
116116
DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
117117
uint64_t Address, const void *Decoder);
118-
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
118+
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
119119
uint64_t Address,
120120
const void *Decoder);
121121
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
122122
uint64_t Address,
123123
const void *Decoder);
124-
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
124+
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
125125
uint64_t Address,
126126
const void *Decoder);
127127
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -481,10 +481,10 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
481481
return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
482482
}
483483

484-
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
485-
uint64_t /*Address*/,
486-
const void *Decoder) {
487-
static const MCPhysReg VecRegDecoderTable[] = {
484+
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
485+
uint64_t /*Address*/,
486+
const void *Decoder) {
487+
static const MCPhysReg HvxVRDecoderTable[] = {
488488
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
489489
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
490490
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
@@ -493,7 +493,7 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
493493
Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
494494
Hexagon::V30, Hexagon::V31};
495495

496-
return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable);
496+
return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
497497
}
498498

499499
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -517,16 +517,16 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(
517517
return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
518518
}
519519

520-
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
521-
uint64_t /*Address*/,
522-
const void *Decoder) {
523-
static const MCPhysReg VecDblRegDecoderTable[] = {
520+
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
521+
uint64_t /*Address*/,
522+
const void *Decoder) {
523+
static const MCPhysReg HvxWRDecoderTable[] = {
524524
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
525525
Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
526526
Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
527527
Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
528528

529-
return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable));
529+
return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
530530
}
531531

532532
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
@@ -538,13 +538,13 @@ static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
538538
return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
539539
}
540540

541-
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
542-
uint64_t /*Address*/,
543-
const void *Decoder) {
544-
static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
545-
Hexagon::Q2, Hexagon::Q3};
541+
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
542+
uint64_t /*Address*/,
543+
const void *Decoder) {
544+
static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
545+
Hexagon::Q2, Hexagon::Q3};
546546

547-
return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable);
547+
return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
548548
}
549549

550550
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,

‎llvm/lib/Target/Hexagon/Hexagon.td

+3
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,9 @@ def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
4444
def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">,
4545
AssemblerPredicate<"ExtensionHVX">;
4646

47+
def Hvx64 : HwMode<"+hvx,-hvx-double">;
48+
def Hvx128 : HwMode<"+hvx,+hvx-double">;
49+
4750
//===----------------------------------------------------------------------===//
4851
// Classes used for relation maps.
4952
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp

+3-82
Original file line numberDiff line numberDiff line change
@@ -281,10 +281,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
281281
MCInst &MappedInst = static_cast <MCInst &>(Inst);
282282
const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
283283
const MachineFunction &MF = *MI.getParent()->getParent();
284-
const auto &HST = MF.getSubtarget<HexagonSubtarget>();
285-
const auto &VecRC = HST.useHVXSglOps() ? Hexagon::VectorRegsRegClass
286-
: Hexagon::VectorRegs128BRegClass;
287-
unsigned VectorSize = HST.getRegisterInfo()->getSpillSize(VecRC);
284+
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
285+
unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
288286

289287
switch (Inst.getOpcode()) {
290288
default: return;
@@ -605,8 +603,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
605603
return;
606604
}
607605

608-
case Hexagon::V6_vd0:
609-
case Hexagon::V6_vd0_128B: {
606+
case Hexagon::V6_vd0: {
610607
MCInst TmpInst;
611608
assert(Inst.getOperand(0).isReg() &&
612609
"Expected register and none was found");
@@ -626,13 +623,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
626623
case Hexagon::V6_vL32b_nt_pi:
627624
case Hexagon::V6_vL32b_nt_tmp_pi:
628625
case Hexagon::V6_vL32b_tmp_pi:
629-
case Hexagon::V6_vL32Ub_pi_128B:
630-
case Hexagon::V6_vL32b_cur_pi_128B:
631-
case Hexagon::V6_vL32b_nt_cur_pi_128B:
632-
case Hexagon::V6_vL32b_pi_128B:
633-
case Hexagon::V6_vL32b_nt_pi_128B:
634-
case Hexagon::V6_vL32b_nt_tmp_pi_128B:
635-
case Hexagon::V6_vL32b_tmp_pi_128B:
636626
MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
637627
return;
638628

@@ -643,13 +633,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
643633
case Hexagon::V6_vL32b_nt_cur_ai:
644634
case Hexagon::V6_vL32b_nt_tmp_ai:
645635
case Hexagon::V6_vL32b_tmp_ai:
646-
case Hexagon::V6_vL32Ub_ai_128B:
647-
case Hexagon::V6_vL32b_ai_128B:
648-
case Hexagon::V6_vL32b_cur_ai_128B:
649-
case Hexagon::V6_vL32b_nt_ai_128B:
650-
case Hexagon::V6_vL32b_nt_cur_ai_128B:
651-
case Hexagon::V6_vL32b_nt_tmp_ai_128B:
652-
case Hexagon::V6_vL32b_tmp_ai_128B:
653636
MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
654637
return;
655638

@@ -658,11 +641,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
658641
case Hexagon::V6_vS32b_nt_new_pi:
659642
case Hexagon::V6_vS32b_nt_pi:
660643
case Hexagon::V6_vS32b_pi:
661-
case Hexagon::V6_vS32Ub_pi_128B:
662-
case Hexagon::V6_vS32b_new_pi_128B:
663-
case Hexagon::V6_vS32b_nt_new_pi_128B:
664-
case Hexagon::V6_vS32b_nt_pi_128B:
665-
case Hexagon::V6_vS32b_pi_128B:
666644
MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
667645
return;
668646

@@ -671,11 +649,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
671649
case Hexagon::V6_vS32b_new_ai:
672650
case Hexagon::V6_vS32b_nt_ai:
673651
case Hexagon::V6_vS32b_nt_new_ai:
674-
case Hexagon::V6_vS32Ub_ai_128B:
675-
case Hexagon::V6_vS32b_ai_128B:
676-
case Hexagon::V6_vS32b_new_ai_128B:
677-
case Hexagon::V6_vS32b_nt_ai_128B:
678-
case Hexagon::V6_vS32b_nt_new_ai_128B:
679652
MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
680653
return;
681654

@@ -691,18 +664,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
691664
case Hexagon::V6_vL32b_pred_pi:
692665
case Hexagon::V6_vL32b_tmp_npred_pi:
693666
case Hexagon::V6_vL32b_tmp_pred_pi:
694-
case Hexagon::V6_vL32b_cur_npred_pi_128B:
695-
case Hexagon::V6_vL32b_cur_pred_pi_128B:
696-
case Hexagon::V6_vL32b_npred_pi_128B:
697-
case Hexagon::V6_vL32b_nt_cur_npred_pi_128B:
698-
case Hexagon::V6_vL32b_nt_cur_pred_pi_128B:
699-
case Hexagon::V6_vL32b_nt_npred_pi_128B:
700-
case Hexagon::V6_vL32b_nt_pred_pi_128B:
701-
case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B:
702-
case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B:
703-
case Hexagon::V6_vL32b_pred_pi_128B:
704-
case Hexagon::V6_vL32b_tmp_npred_pi_128B:
705-
case Hexagon::V6_vL32b_tmp_pred_pi_128B:
706667
MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
707668
return;
708669

@@ -718,18 +679,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
718679
case Hexagon::V6_vL32b_pred_ai:
719680
case Hexagon::V6_vL32b_tmp_npred_ai:
720681
case Hexagon::V6_vL32b_tmp_pred_ai:
721-
case Hexagon::V6_vL32b_cur_npred_ai_128B:
722-
case Hexagon::V6_vL32b_cur_pred_ai_128B:
723-
case Hexagon::V6_vL32b_npred_ai_128B:
724-
case Hexagon::V6_vL32b_nt_cur_npred_ai_128B:
725-
case Hexagon::V6_vL32b_nt_cur_pred_ai_128B:
726-
case Hexagon::V6_vL32b_nt_npred_ai_128B:
727-
case Hexagon::V6_vL32b_nt_pred_ai_128B:
728-
case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B:
729-
case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B:
730-
case Hexagon::V6_vL32b_pred_ai_128B:
731-
case Hexagon::V6_vL32b_tmp_npred_ai_128B:
732-
case Hexagon::V6_vL32b_tmp_pred_ai_128B:
733682
MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
734683
return;
735684

@@ -747,20 +696,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
747696
case Hexagon::V6_vS32b_nt_qpred_pi:
748697
case Hexagon::V6_vS32b_pred_pi:
749698
case Hexagon::V6_vS32b_qpred_pi:
750-
case Hexagon::V6_vS32Ub_npred_pi_128B:
751-
case Hexagon::V6_vS32Ub_pred_pi_128B:
752-
case Hexagon::V6_vS32b_new_npred_pi_128B:
753-
case Hexagon::V6_vS32b_new_pred_pi_128B:
754-
case Hexagon::V6_vS32b_npred_pi_128B:
755-
case Hexagon::V6_vS32b_nqpred_pi_128B:
756-
case Hexagon::V6_vS32b_nt_new_npred_pi_128B:
757-
case Hexagon::V6_vS32b_nt_new_pred_pi_128B:
758-
case Hexagon::V6_vS32b_nt_npred_pi_128B:
759-
case Hexagon::V6_vS32b_nt_nqpred_pi_128B:
760-
case Hexagon::V6_vS32b_nt_pred_pi_128B:
761-
case Hexagon::V6_vS32b_nt_qpred_pi_128B:
762-
case Hexagon::V6_vS32b_pred_pi_128B:
763-
case Hexagon::V6_vS32b_qpred_pi_128B:
764699
MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
765700
return;
766701

@@ -778,20 +713,6 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
778713
case Hexagon::V6_vS32b_nt_qpred_ai:
779714
case Hexagon::V6_vS32b_pred_ai:
780715
case Hexagon::V6_vS32b_qpred_ai:
781-
case Hexagon::V6_vS32Ub_npred_ai_128B:
782-
case Hexagon::V6_vS32Ub_pred_ai_128B:
783-
case Hexagon::V6_vS32b_new_npred_ai_128B:
784-
case Hexagon::V6_vS32b_new_pred_ai_128B:
785-
case Hexagon::V6_vS32b_npred_ai_128B:
786-
case Hexagon::V6_vS32b_nqpred_ai_128B:
787-
case Hexagon::V6_vS32b_nt_new_npred_ai_128B:
788-
case Hexagon::V6_vS32b_nt_new_pred_ai_128B:
789-
case Hexagon::V6_vS32b_nt_npred_ai_128B:
790-
case Hexagon::V6_vS32b_nt_nqpred_ai_128B:
791-
case Hexagon::V6_vS32b_nt_pred_ai_128B:
792-
case Hexagon::V6_vS32b_nt_qpred_ai_128B:
793-
case Hexagon::V6_vS32b_pred_ai_128B:
794-
case Hexagon::V6_vS32b_qpred_ai_128B:
795716
MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
796717
return;
797718
}

‎llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp

+5-12
Original file line numberDiff line numberDiff line change
@@ -420,8 +420,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
420420

421421
switch (RC->getID()) {
422422
case Hexagon::DoubleRegsRegClassID:
423-
case Hexagon::VecDblRegsRegClassID:
424-
case Hexagon::VecDblRegs128BRegClassID:
423+
case Hexagon::HvxWRRegClassID:
425424
Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
426425
if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
427426
Begin = Width;
@@ -918,12 +917,9 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
918917
case Hexagon::DoubleRegsRegClassID:
919918
VerifySR(RC, RR.Sub);
920919
return &Hexagon::IntRegsRegClass;
921-
case Hexagon::VecDblRegsRegClassID:
920+
case Hexagon::HvxWRRegClassID:
922921
VerifySR(RC, RR.Sub);
923-
return &Hexagon::VectorRegsRegClass;
924-
case Hexagon::VecDblRegs128BRegClassID:
925-
VerifySR(RC, RR.Sub);
926-
return &Hexagon::VectorRegs128BRegClass;
922+
return &Hexagon::HvxVRRegClass;
927923
}
928924
return nullptr;
929925
}
@@ -1627,8 +1623,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
16271623
}
16281624

16291625
if (FRC == &Hexagon::DoubleRegsRegClass ||
1630-
FRC == &Hexagon::VecDblRegsRegClass ||
1631-
FRC == &Hexagon::VecDblRegs128BRegClass) {
1626+
FRC == &Hexagon::HvxWRRegClass) {
16321627
// Try to generate REG_SEQUENCE.
16331628
unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
16341629
unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
@@ -1665,7 +1660,6 @@ bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
16651660
case Hexagon::A2_tfrp:
16661661
case Hexagon::A2_combinew:
16671662
case Hexagon::V6_vcombine:
1668-
case Hexagon::V6_vcombine_128B:
16691663
return NoConv;
16701664
default:
16711665
break;
@@ -1704,8 +1698,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
17041698
break;
17051699
}
17061700
case Hexagon::A2_combinew:
1707-
case Hexagon::V6_vcombine:
1708-
case Hexagon::V6_vcombine_128B: {
1701+
case Hexagon::V6_vcombine: {
17091702
const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
17101703
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
17111704
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);

‎llvm/lib/Target/Hexagon/HexagonBitTracker.cpp

+1-3
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,7 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
102102
bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
103103
switch (ID) {
104104
case DoubleRegsRegClassID:
105-
case VecDblRegsRegClassID:
106-
case VecDblRegs128BRegClassID:
105+
case HvxWRRegClassID:
107106
return IsSubLo ? BT::BitMask(0, RW-1)
108107
: BT::BitMask(RW, 2*RW-1);
109108
default:
@@ -703,7 +702,6 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
703702
case A4_combineri:
704703
case A2_combinew:
705704
case V6_vcombine:
706-
case V6_vcombine_128B:
707705
assert(W0 % 2 == 0);
708706
return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
709707
case A2_combine_ll:

‎llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp

+5-13
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,6 @@ static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
161161
}
162162

163163
case Hexagon::V6_vassign:
164-
case Hexagon::V6_vassign_128B:
165164
return true;
166165

167166
default:
@@ -231,8 +230,7 @@ static bool isEvenReg(unsigned Reg) {
231230
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
232231
if (Hexagon::IntRegsRegClass.contains(Reg))
233232
return (Reg - Hexagon::R0) % 2 == 0;
234-
if (Hexagon::VectorRegsRegClass.contains(Reg) ||
235-
Hexagon::VectorRegs128BRegClass.contains(Reg))
233+
if (Hexagon::HvxVRRegClass.contains(Reg))
236234
return (Reg - Hexagon::V0) % 2 == 0;
237235
llvm_unreachable("Invalid register");
238236
}
@@ -593,12 +591,9 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
593591
if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
594592
SuperRC = &Hexagon::DoubleRegsRegClass;
595593
SubLo = Hexagon::isub_lo;
596-
} else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) {
594+
} else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {
597595
assert(ST->useHVXOps());
598-
if (ST->useHVXSglOps())
599-
SuperRC = &Hexagon::VecDblRegsRegClass;
600-
else
601-
SuperRC = &Hexagon::VecDblRegs128BRegClass;
596+
SuperRC = &Hexagon::HvxWRRegClass;
602597
SubLo = Hexagon::vsub_lo;
603598
} else
604599
llvm_unreachable("Unexpected register class");
@@ -875,12 +870,9 @@ void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
875870
unsigned NewOpc;
876871
if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
877872
NewOpc = Hexagon::A2_combinew;
878-
} else if (Hexagon::VecDblRegsRegClass.contains(DoubleDestReg)) {
873+
} else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {
879874
assert(ST->useHVXOps());
880-
if (ST->useHVXSglOps())
881-
NewOpc = Hexagon::V6_vcombine;
882-
else
883-
NewOpc = Hexagon::V6_vcombine_128B;
875+
NewOpc = Hexagon::V6_vcombine;
884876
} else
885877
llvm_unreachable("Unexpected register");
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