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TNorthoverTNorthover
committedJul 22, 2016
GlobalISel: implement legalization pass, with just one transformation.
This adds the actual MachineLegalizeHelper to do the work and a trivial pass wrapper that legalizes all instructions in a MachineFunction. Currently the only transformation supported is splitting up a vector G_ADD into one acting on smaller vectors. llvm-svn: 276461
1 parent e4a4f33 commit 33b07d6

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+554
-16
lines changed
 

‎llvm/include/llvm/CodeGen/GlobalISel/GISelAccessor.h

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@@ -17,6 +17,7 @@
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namespace llvm {
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class CallLowering;
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class MachineLegalizer;
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class RegisterBankInfo;
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/// The goal of this helper class is to gather the accessor to all
@@ -27,6 +28,9 @@ class RegisterBankInfo;
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struct GISelAccessor {
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virtual ~GISelAccessor() {}
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virtual const CallLowering *getCallLowering() const { return nullptr;}
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virtual const MachineLegalizer *getMachineLegalizer() const {
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return nullptr;
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}
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virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr;}
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};
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} // End namespace llvm;

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

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@@ -80,7 +80,7 @@ class MachineIRBuilder {
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/// Set the insertion point to before (\p Before = true) or after
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/// (\p Before = false) \p MI.
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/// \pre MI must be in getMF().
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void setInstr(MachineInstr &MI, bool Before = false);
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void setInstr(MachineInstr &MI, bool Before = true);
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/// @}
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/// Set the debug location to \p DL for all the next build instructions.
@@ -152,6 +152,37 @@ class MachineIRBuilder {
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/// \return The newly created instruction.
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MachineInstr *buildFrameIndex(LLT Ty, unsigned Res, int Idx);
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/// Build and insert \p Res<def> = G_ADD \p Ty \p Op0, \p Op1
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///
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/// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
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/// truncated to their width.
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///
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/// \pre setBasicBlock or setMI must have been called.
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///
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/// \return The newly created instruction.
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MachineInstr *buildAdd(LLT Ty, unsigned Res, unsigned Op0, unsigned Op1);
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/// Build and insert `Res0<def>, ... = G_EXTRACT Ty Src, Idx0, ...`.
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///
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/// If \p Ty has size N bits, G_EXTRACT sets \p Res[0] to bits `[Idxs[0],
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/// Idxs[0] + N)` of \p Src and similarly for subsequent bit-indexes.
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///
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/// \pre setBasicBlock or setMI must have been called.
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///
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/// \return The newly created instruction.
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MachineInstr *buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src,
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ArrayRef<unsigned> Indexes);
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/// Build and insert \p Res<def> = G_SEQUENCE \p Ty \p Ops[0], ...
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///
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/// G_SEQUENCE concatenates each element in Ops into a single register, where
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/// Ops[0] starts at bit 0 of \p Res.
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///
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/// \pre setBasicBlock or setMI must have been called.
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/// \pre The sum of the input sizes must equal the result's size.
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///
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/// \return The newly created instruction.
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MachineInstr *buildSequence(LLT Ty, unsigned Res, ArrayRef<unsigned> Ops);
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};
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} // End namespace llvm.

‎llvm/include/llvm/CodeGen/GlobalISel/MachineLegalizeHelper.h

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@@ -0,0 +1,92 @@
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//== llvm/CodeGen/GlobalISel/MachineLegalizeHelper.h ----------- -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file A pass to convert the target-illegal operations created by IR -> MIR
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/// translation into ones the target expects to be able to select. This may
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/// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
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/// G_ADD <4 x i16>.
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///
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/// The MachineLegalizeHelper class is where most of the work happens, and is
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/// designed to be callable from other passes that find themselves with an
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/// illegal instruction.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZEHELPER_H
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#define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZEHELPER_H
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LowLevelType.h"
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namespace llvm {
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// Forward declarations.
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class MachineLegalizeInfo;
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class MachineLegalizer;
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class MachineRegisterInfo;
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class MachineLegalizeHelper {
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public:
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enum LegalizeResult {
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/// Instruction was already legal and no change was made to the
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/// MachineFunction.
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AlreadyLegal,
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/// Instruction has been legalized and the MachineFunction changed.
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Legalized,
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/// Some kind of error has occurred and we could not legalize this
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/// instruction.
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UnableToLegalize,
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};
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MachineLegalizeHelper(MachineFunction &MF);
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/// Replace \p MI by a sequence of legal instructions that can implement the
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/// same operation. Note that this means \p MI may be deleted, so any iterator
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/// steps should be performed before calling this function. \p Helper should
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/// be initialized to the MachineFunction containing \p MI.
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///
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/// Considered as an opaque blob, the legal code will use and define the same
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/// registers as \p MI.
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LegalizeResult legalizeInstr(MachineInstr &MI,
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const MachineLegalizer &Legalizer);
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/// Legalize an instruction by reducing the width of the underlying scalar
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/// type.
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LegalizeResult narrowScalar(MachineInstr &MI, LLT NarrowTy);
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/// Legalize an instruction by performing the operation on a wider scalar type
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/// (for example a 16-bit addition can be safely performed at 32-bits
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/// precision, ignoring the unused bits).
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LegalizeResult widenScalar(MachineInstr &MI, LLT WideTy);
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/// Legalize a vector instruction by splitting into multiple components, each
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/// acting on the same scalar type as the original but with fewer elements.
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LegalizeResult fewerElementsVector(MachineInstr &MI, LLT NarrowTy);
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/// Legalize a vector instruction by increasing the number of vector elements
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/// involved and ignoring the added elements later.
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LegalizeResult moreElementsVector(MachineInstr &MI, LLT WideTy);
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private:
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/// Helper function to split a wide generic register into bitwise blocks with
81+
/// the given Type (which implies the number of blocks needed). The generic
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/// registers created are appended to Ops, starting at bit 0 of Reg.
83+
void extractParts(unsigned Reg, LLT Ty, int NumParts,
84+
SmallVectorImpl<unsigned> &Ops);
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86+
MachineIRBuilder MIRBuilder;
87+
MachineRegisterInfo &MRI;
88+
};
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} // End namespace llvm.
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#endif

‎llvm/include/llvm/CodeGen/GlobalISel/MachineLegalizePass.h

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//== llvm/CodeGen/GlobalISel/MachineLegalizePass.h ------------- -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file A pass to convert the target-illegal operations created by IR -> MIR
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/// translation into ones the target expects to be able to select. This may
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/// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
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/// G_ADD <4 x i16>.
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///
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/// The LegalizeHelper class is where most of the work happens, and is designed
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/// to be callable from other passes that find themselves with an illegal
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/// instruction.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZEMACHINEIRPASS_H
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#define LLVM_CODEGEN_GLOBALISEL_LEGALIZEMACHINEIRPASS_H
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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namespace llvm {
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class MachineLegalizePass : public MachineFunctionPass {
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public:
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static char ID;
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private:
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/// Initialize the field members using \p MF.
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void init(MachineFunction &MF);
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public:
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// Ctor, nothing fancy.
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MachineLegalizePass();
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const char *getPassName() const override {
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return "MachineLegalizePass";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // End namespace llvm.
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#endif

‎llvm/include/llvm/CodeGen/GlobalISel/MachineLegalizer.h

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@@ -71,17 +71,6 @@ class MachineLegalizer {
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MachineLegalizer();
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74-
/// Replace \p MI by a sequence of legal instructions that can implement the
75-
/// same operation. Note that this means \p MI may be deleted, so any iterator
76-
/// steps should be performed before calling this function.
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///
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/// Considered as an opaque blob, the legal code will use and define the same
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/// registers as \p MI.
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///
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/// \returns true if the function is modified, false if the instruction was
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/// already legal.
83-
bool legalizeInstr(MachineInstr &MI) const;
84-
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/// Compute any ancillary tables needed to quickly decide how an operation
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/// should be handled. This must be called after all "set*Action"methods but
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/// before any query is made or incorrect results may be returned.

‎llvm/include/llvm/CodeGen/TargetPassConfig.h

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@@ -217,6 +217,14 @@ class TargetPassConfig : public ImmutablePass {
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/// LLVM code to machine instructions with possibly generic opcodes.
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virtual bool addIRTranslator() { return true; }
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/// This method may be implemented by targets that want to run passes
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/// immediately before legalization.
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virtual void addPreLegalizeMachineIR() {}
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/// This method should install a legalize pass, which converts the instruction
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/// sequence into one that can be selected by the target.
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virtual bool addLegalizeMachineIR() { return true; }
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/// This method may be implemented by targets that want to run passes
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/// immediately before the register bank selection.
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virtual void addPreRegBankSelect() {}

‎llvm/include/llvm/InitializePasses.h

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@@ -214,6 +214,7 @@ void initializeMachineCopyPropagationPass(PassRegistry&);
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void initializeMachineDominanceFrontierPass(PassRegistry&);
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void initializeMachineDominatorTreePass(PassRegistry&);
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void initializeMachineFunctionPrinterPassPass(PassRegistry&);
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void initializeMachineLegalizePassPass(PassRegistry&);
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void initializeMachineLICMPass(PassRegistry&);
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void initializeMachineLoopInfoPass(PassRegistry&);
219220
void initializeMachineModuleInfoPass(PassRegistry&);

‎llvm/include/llvm/Target/GenericOpcodes.td

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@@ -57,6 +57,27 @@ def G_OR : Instruction {
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let isCommutable = 1;
5858
}
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//------------------------------------------------------------------------------
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// Variadic ops
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//------------------------------------------------------------------------------
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// Extract multiple registers specified size, starting from blocks given by
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// indexes. This will almost certainly be mapped to sub-register COPYs after
66+
// register banks have been selected.
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def G_EXTRACT : Instruction {
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let OutOperandList = (outs variable_ops);
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let InOperandList = (ins variable_ops);
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let hasSideEffects = 0;
71+
}
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// Combine a sequence of generic vregs into a single larger value (starting at
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// bit 0).
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def G_SEQUENCE : Instruction {
76+
let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins variable_ops);
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let hasSideEffects = 0;
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}
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//------------------------------------------------------------------------------
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// Branches.
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//------------------------------------------------------------------------------

‎llvm/include/llvm/Target/TargetOpcodes.def

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@@ -172,6 +172,14 @@ HANDLE_TARGET_OPCODE(G_OR)
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/// stack-based object.
173173
HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
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175+
/// Generic instruction to extract blocks of bits from the register given
176+
/// (typically a sub-register COPY after instruction selection).
177+
HANDLE_TARGET_OPCODE(G_EXTRACT)
178+
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/// Generic instruction to paste a variable number of components together into a
180+
/// larger register.
181+
HANDLE_TARGET_OPCODE(G_SEQUENCE)
182+
175183
/// Generic BRANCH instruction. This is an unconditional branch.
176184
HANDLE_TARGET_OPCODE(G_BR)
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‎llvm/include/llvm/Target/TargetSubtargetInfo.h

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@@ -27,6 +27,7 @@ class CallLowering;
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class DataLayout;
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class MachineFunction;
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class MachineInstr;
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class MachineLegalizer;
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class RegisterBankInfo;
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class SDep;
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class SUnit;
@@ -94,6 +95,10 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
9495
return nullptr;
9596
}
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virtual const MachineLegalizer *getMachineLegalizer() const {
99+
return nullptr;
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}
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/// getRegisterInfo - If register information is available, return it. If
98103
/// not, return null.
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///

‎llvm/lib/CodeGen/GlobalISel/CMakeLists.txt

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set(GLOBAL_ISEL_FILES
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IRTranslator.cpp
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MachineIRBuilder.cpp
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MachineLegalizeHelper.cpp
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MachineLegalizePass.cpp
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MachineLegalizer.cpp
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RegBankSelect.cpp
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RegisterBank.cpp

‎llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp

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@@ -25,6 +25,7 @@ void llvm::initializeGlobalISel(PassRegistry &Registry) {
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void llvm::initializeGlobalISel(PassRegistry &Registry) {
2727
initializeIRTranslatorPass(Registry);
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initializeMachineLegalizePassPass(Registry);
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initializeRegBankSelectPass(Registry);
2930
}
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#endif // LLVM_BUILD_GLOBAL_ISEL

‎llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

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@@ -110,3 +110,35 @@ MachineInstr *MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res, int Idx) {
110110
MIB.addImm(Idx);
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return NewMI;
112112
}
113+
114+
MachineInstr *MachineIRBuilder::buildAdd(LLT Ty, unsigned Res, unsigned Op0,
115+
unsigned Op1) {
116+
return buildInstr(TargetOpcode::G_ADD, Ty, Res, Op0, Op1);
117+
}
118+
119+
MachineInstr *MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results,
120+
unsigned Src,
121+
ArrayRef<unsigned> Indexes) {
122+
assert(Results.size() == Indexes.size() && "inconsistent number of regs");
123+
124+
MachineInstr *NewMI = buildInstr(TargetOpcode::G_EXTRACT, Ty);
125+
auto MIB = MachineInstrBuilder(getMF(), NewMI);
126+
for (auto Res : Results)
127+
MIB.addReg(Res, RegState::Define);
128+
129+
MIB.addReg(Src);
130+
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for (auto Idx : Indexes)
132+
MIB.addImm(Idx);
133+
return NewMI;
134+
}
135+
136+
MachineInstr *MachineIRBuilder::buildSequence(LLT Ty, unsigned Res,
137+
ArrayRef<unsigned> Ops) {
138+
MachineInstr *NewMI = buildInstr(TargetOpcode::G_SEQUENCE, Ty);
139+
auto MIB = MachineInstrBuilder(getMF(), NewMI);
140+
MIB.addReg(Res, RegState::Define);
141+
for (auto Op : Ops)
142+
MIB.addReg(Op);
143+
return NewMI;
144+
}

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