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author
Simon Dardis
committedJun 14, 2016
[mips][atomics] Fix atomic instruction descriptions and uses.
PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
·
llvmorg-21-initllvmorg-3.9.0-rc1
1 parent 6465008 commit 4fbf76f

9 files changed

+127
-32
lines changed
 

‎llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

+23
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ class MipsDisassembler : public MCDisassembler {
3939
IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
4040
IsBigEndian(IsBigEndian) {}
4141

42+
bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
4243
bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
4344
bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
4445
bool hasMips32r6() const {
@@ -48,6 +49,8 @@ class MipsDisassembler : public MCDisassembler {
4849

4950
bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
5051

52+
bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
53+
5154
bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
5255

5356
bool hasCOP3() const {
@@ -1049,6 +1052,16 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
10491052
}
10501053
}
10511054

1055+
if (hasMips32r6() && isPTR64()) {
1056+
DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1057+
Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1058+
Address, this, STI);
1059+
if (Result != MCDisassembler::Fail) {
1060+
Size = 4;
1061+
return Result;
1062+
}
1063+
}
1064+
10521065
if (hasMips32r6()) {
10531066
DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
10541067
Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
@@ -1059,6 +1072,16 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
10591072
}
10601073
}
10611074

1075+
if (hasMips2() && isPTR64()) {
1076+
DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1077+
Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1078+
Address, this, STI);
1079+
if (Result != MCDisassembler::Fail) {
1080+
Size = 4;
1081+
return Result;
1082+
}
1083+
}
1084+
10621085
if (hasCnMips()) {
10631086
DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
10641087
Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,

‎llvm/lib/Target/Mips/Mips.td

+5
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@ class PredicateControl {
2424
list<Predicate> EncodingPredicates = [];
2525
// Predicates for the GPR size such as IsGP64bit
2626
list<Predicate> GPRPredicates = [];
27+
// Predicates for the PTR size such as IsPTR64bit
28+
list<Predicate> PTRPredicates = [];
2729
// Predicates for the FGR size and layout such as IsFP64bit
2830
list<Predicate> FGRPredicates = [];
2931
// Predicates for the instruction group membership such as ISA's and ASE's
@@ -34,6 +36,7 @@ class PredicateControl {
3436
list<Predicate> AdditionalPredicates = [];
3537
list<Predicate> Predicates = !listconcat(EncodingPredicates,
3638
GPRPredicates,
39+
PTRPredicates,
3740
FGRPredicates,
3841
InsnPredicates,
3942
HardFloatPredicate,
@@ -62,6 +65,8 @@ def MipsInstrInfo : InstrInfo;
6265

6366
def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
6467
"Disable SVR4-style position-independent code">;
68+
def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
69+
"Pointers are 64-bit wide">;
6570
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
6671
"General Purpose Registers are 64-bit wide">;
6772
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

+2-2
Original file line numberDiff line numberDiff line change
@@ -794,7 +794,7 @@ def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
794794
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
795795
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
796796
let AdditionalPredicates = [NotInMicroMips] in {
797-
def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
797+
def LL_R6 : LL_R6_ENC, LL_R6_DESC, PTR_32, ISA_MIPS32R6;
798798
}
799799
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
800800
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
@@ -828,7 +828,7 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
828828
let AdditionalPredicates = [NotInMicroMips] in {
829829
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
830830
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
831-
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
831+
def SC_R6 : SC_R6_ENC, SC_R6_DESC, PTR_32, ISA_MIPS32R6;
832832
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
833833
}
834834
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;

‎llvm/lib/Target/Mips/Mips64InstrInfo.td

+8
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,14 @@ def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
214214
def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
215215
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
216216

217+
let AdditionalPredicates = [NotInMicroMips],
218+
DecoderNamespace = "Mips32_64_PTR64" in {
219+
def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64,
220+
ISA_MIPS2_NOT_32R6_64R6;
221+
def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64,
222+
ISA_MIPS2_NOT_32R6_64R6;
223+
}
224+
217225
/// Jump and Branch Instructions
218226
let isCodeGenOnly = 1 in {
219227
def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;

‎llvm/lib/Target/Mips/Mips64r6InstrInfo.td

+7
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,8 @@ class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
8888
list<Register> Defs = [AT];
8989
}
9090

91+
class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
92+
class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
9193
//===----------------------------------------------------------------------===//
9294
//
9395
// Instruction Definitions
@@ -123,6 +125,11 @@ let DecoderNamespace = "Mips32r6_64r6_GP64" in {
123125
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
124126
def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
125127
}
128+
let AdditionalPredicates = [NotInMicroMips],
129+
DecoderNamespace = "Mips32r6_64r6_PTR64" in {
130+
def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
131+
def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
132+
}
126133
let isCodeGenOnly = 1 in {
127134
def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
128135
def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

+46-18
Original file line numberDiff line numberDiff line change
@@ -1107,19 +1107,23 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
11071107
MachineRegisterInfo &RegInfo = MF->getRegInfo();
11081108
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
11091109
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1110+
const bool ArePtrs64bit = ABI.ArePtrs64bit();
11101111
DebugLoc DL = MI->getDebugLoc();
11111112
unsigned LL, SC, AND, NOR, ZERO, BEQ;
11121113

1113-
// FIXME: The below code should check for the ISA to emit the correct 64bit
1114-
// operations when the size is 4.
11151114
if (Size == 4) {
11161115
if (isMicroMips) {
11171116
LL = Mips::LL_MM;
11181117
SC = Mips::SC_MM;
11191118
} else {
1120-
LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1121-
SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1119+
LL = Subtarget.hasMips32r6()
1120+
? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1121+
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1122+
SC = Subtarget.hasMips32r6()
1123+
? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1124+
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
11221125
}
1126+
11231127
AND = Mips::AND;
11241128
NOR = Mips::NOR;
11251129
ZERO = Mips::ZERO;
@@ -1226,7 +1230,7 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
12261230
MachineFunction *MF = BB->getParent();
12271231
MachineRegisterInfo &RegInfo = MF->getRegInfo();
12281232
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1229-
bool ArePtrs64bit = ABI.ArePtrs64bit();
1233+
const bool ArePtrs64bit = ABI.ArePtrs64bit();
12301234
const TargetRegisterClass *RCp =
12311235
getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
12321236
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@@ -1254,6 +1258,17 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
12541258
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
12551259
unsigned Success = RegInfo.createVirtualRegister(RC);
12561260

1261+
unsigned LL, SC;
1262+
if (isMicroMips) {
1263+
LL = Mips::LL_MM;
1264+
SC = Mips::SC_MM;
1265+
} else {
1266+
LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1267+
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1268+
SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1269+
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1270+
}
1271+
12571272
// insert new blocks after the current block
12581273
const BasicBlock *LLVM_BB = BB->getBasicBlock();
12591274
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
@@ -1326,7 +1341,6 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
13261341
// beq success,$0,loopMBB
13271342

13281343
BB = loopMBB;
1329-
unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
13301344
BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
13311345
if (Nand) {
13321346
// and andres, oldval, incr2
@@ -1350,7 +1364,6 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
13501364
.addReg(OldVal).addReg(Mask2);
13511365
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
13521366
.addReg(MaskedOldVal0).addReg(NewVal);
1353-
unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
13541367
BuildMI(BB, DL, TII->get(SC), Success)
13551368
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
13561369
BuildMI(BB, DL, TII->get(Mips::BEQ))
@@ -1382,17 +1395,23 @@ MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
13821395
MachineRegisterInfo &RegInfo = MF->getRegInfo();
13831396
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
13841397
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1398+
const bool ArePtrs64bit = ABI.ArePtrs64bit();
13851399
DebugLoc DL = MI->getDebugLoc();
13861400
unsigned LL, SC, ZERO, BNE, BEQ;
13871401

1388-
if (Size == 4) {
1389-
if (isMicroMips) {
1390-
LL = Mips::LL_MM;
1391-
SC = Mips::SC_MM;
1392-
} else {
1393-
LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1394-
SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1395-
}
1402+
if (Size == 4) {
1403+
if (isMicroMips) {
1404+
LL = Mips::LL_MM;
1405+
SC = Mips::SC_MM;
1406+
} else {
1407+
LL = Subtarget.hasMips32r6()
1408+
? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1409+
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1410+
SC = Subtarget.hasMips32r6()
1411+
? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1412+
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1413+
}
1414+
13961415
ZERO = Mips::ZERO;
13971416
BNE = Mips::BNE;
13981417
BEQ = Mips::BEQ;
@@ -1467,7 +1486,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
14671486
MachineFunction *MF = BB->getParent();
14681487
MachineRegisterInfo &RegInfo = MF->getRegInfo();
14691488
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1470-
bool ArePtrs64bit = ABI.ArePtrs64bit();
1489+
const bool ArePtrs64bit = ABI.ArePtrs64bit();
14711490
const TargetRegisterClass *RCp =
14721491
getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
14731492
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@@ -1495,6 +1514,17 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
14951514
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
14961515
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
14971516
unsigned Success = RegInfo.createVirtualRegister(RC);
1517+
unsigned LL, SC;
1518+
1519+
if (isMicroMips) {
1520+
LL = Mips::LL_MM;
1521+
SC = Mips::SC_MM;
1522+
} else {
1523+
LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1524+
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1525+
SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1526+
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1527+
}
14981528

14991529
// insert new blocks after the current block
15001530
const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1568,7 +1598,6 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
15681598
// and maskedoldval0,oldval,mask
15691599
// bne maskedoldval0,shiftedcmpval,sinkMBB
15701600
BB = loop1MBB;
1571-
unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
15721601
BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
15731602
BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
15741603
.addReg(OldVal).addReg(Mask);
@@ -1585,7 +1614,6 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
15851614
.addReg(OldVal).addReg(Mask2);
15861615
BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
15871616
.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1588-
unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
15891617
BuildMI(BB, DL, TII->get(SC), Success)
15901618
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
15911619
BuildMI(BB, DL, TII->get(Mips::BEQ))

‎llvm/lib/Target/Mips/MipsInstrInfo.td

+11-2
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,10 @@ def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
179179
AssemblerPredicate<"FeatureGP64Bit">;
180180
def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
181181
AssemblerPredicate<"!FeatureGP64Bit">;
182+
def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
183+
AssemblerPredicate<"FeaturePTR64Bit">;
184+
def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
185+
AssemblerPredicate<"!FeaturePTR64Bit">;
182186
def HasMips64 : Predicate<"Subtarget->hasMips64()">,
183187
AssemblerPredicate<"FeatureMips64">;
184188
def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
@@ -225,6 +229,9 @@ def HasMSA : Predicate<"Subtarget->hasMSA()">,
225229
class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
226230
class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
227231

232+
class PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; }
233+
class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; }
234+
228235
//===----------------------------------------------------------------------===//
229236
// Mips ISA/ASE membership and instruction group membership adjectives.
230237
// They are mutually exclusive.
@@ -1821,10 +1828,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
18211828
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
18221829
AdditionalPredicates = [NotInMicroMips] in {
18231830
def WAIT : WAIT_FT<"wait">, WAIT_FM;
1831+
}
18241832

1833+
let AdditionalPredicates = [NotInMicroMips] in {
18251834
/// Load-linked, Store-conditional
1826-
def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1827-
def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1835+
def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
1836+
def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
18281837
}
18291838

18301839
/// Jump and Branch Instructions

‎llvm/lib/Target/Mips/MipsSubtarget.h

+5
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
8181
// IsFP64bit - General-purpose registers are 64 bits wide
8282
bool IsGP64bit;
8383

84+
// IsPTR64bit - Pointers are 64 bit wide
85+
bool IsPTR64bit;
86+
8487
// HasVFPU - Processor has a vector floating point unit.
8588
bool HasVFPU;
8689

@@ -223,6 +226,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
223226
bool isGP64bit() const { return IsGP64bit; }
224227
bool isGP32bit() const { return !IsGP64bit; }
225228
unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
229+
bool isPTR64bit() const { return IsPTR64bit; }
230+
bool isPTR32bit() const { return !IsPTR64bit; }
226231
bool isSingleFloat() const { return IsSingleFloat; }
227232
bool hasVFPU() const { return HasVFPU; }
228233
bool inMips16Mode() const { return InMips16Mode; }

‎llvm/test/CodeGen/Mips/atomic.ll

+20-10
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,26 @@
1-
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
2-
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
3-
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
4-
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
5-
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
6-
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
7-
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
8-
; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL-LABEL -check-prefix=MIPS64-ANY -check-prefix=O0
9-
;; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
1+
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s \
2+
; RUN: -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
3+
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s \
4+
; RUN: -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
5+
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s \
6+
; RUN: -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
7+
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s \
8+
; RUN: -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
9+
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s \
10+
; RUN: -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
11+
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s \
12+
; RUN: -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
13+
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s \
14+
; RUN: -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
15+
; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s \
16+
; RUN: -check-prefix=ALL-LABEL -check-prefix=MIPS64-ANY -check-prefix=O0
17+
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | FileCheck %s \
18+
; RUN: -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
1019

1120
; Keep one big-endian check so that we don't reduce testing, but don't add more
1221
; since endianness doesn't affect the body of the atomic operations.
13-
; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
22+
; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s \
23+
; RUN: -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
1424

1525
@x = common global i32 0, align 4
1626

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