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uweiganduweigand
committedApr 1, 2015
[SystemZ] Support transactional execution on zEC12
The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds LLVM support to enable those builtins. In partciular, the patch: - adds the transactional-execution and processor-assist facilities - adds MC support for all instructions provided by those facilities - adds LLVM intrinsics for those instructions and hooks them up for CodeGen - adds CodeGen support to optimize CC return value checking Since this is first use of target-specific intrinsics on the platform, the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and hooks it up in Intrinsics.td. I've also changed Triple::getArchTypePrefix to return "s390" instead of "systemz", since the naming convention for GCC intrinsics uses "s390" on the platform, and it neemed more straight- forward to use the same convention for LLVM IR intrinsics. An associated clang patch makes the intrinsics (and command line switches) available at the source-language level. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td +++ llvm-head/lib/Target/SystemZ/SystemZOperators.td @@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProf def SDT_ZPrefetch : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; +def SDT_ZTBegin : SDTypeProfile<0, 2, + [SDTCisPtrTy<0>, + SDTCisVT<1, i32>]>; //===----------------------------------------------------------------------===// // Node definitions @@ -180,6 +183,15 @@ def z_prefetch : SDNode<"System [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, + [SDNPHasChain, SDNPOutGlue, SDNPMayStore, + SDNPSideEffect]>; +def z_tend : SDNode<"SystemZISD::TEND", SDTNone, + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // Pattern fragments //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td @@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i let Inst{15-0} = BD2; } +class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> + : InstSystemZ<4, outs, ins, asmstr, pattern> { + field bits<32> Inst; + field bits<32> SoftFail = 0; + + bits<16> BD2; + + let Inst{31-16} = op; + let Inst{15-0} = BD2; +} + //===----------------------------------------------------------------------===// // Instruction definitions with semantics //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td +++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1362,6 +1362,60 @@ let Defs = [CC] in { } //===----------------------------------------------------------------------===// +// Transactional execution +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureTransactionalExecution] in { + // Transaction Begin + let hasSideEffects = 1, mayStore = 1, + usesCustomInserter = 1, Defs = [CC] in { + def TBEGIN : InstSIL<0xE560, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbegin\t$BD1, $I2", + [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; + def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + [(z_tbegin_nofloat bdaddr12only:$BD1, + imm32zx16:$I2)]>; + def TBEGINC : InstSIL<0xE561, + (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), + "tbeginc\t$BD1, $I2", + [(int_s390_tbeginc bdaddr12only:$BD1, + imm32zx16:$I2)]>; + } + + // Transaction End + let hasSideEffects = 1, Defs = [CC], BD2 = 0 in + def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; + + // Transaction Abort + let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in + def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), + "tabort\t$BD2", + [(int_s390_tabort bdaddr12only:$BD2)]>; + + // Nontransactional Store + let hasSideEffects = 1 in + def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; + + // Extract Transaction Nesting Depth + let hasSideEffects = 1 in + def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; +} + +//===----------------------------------------------------------------------===// +// Processor assist +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureProcessorAssist] in { + let hasSideEffects = 1, R4 = 0 in + def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), + "ppa\t$R1, $R2, $R3", []>; + def : Pat<(int_s390_ppa_txassist GR32:$src), + (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), + 0, 1)>; +} + +//===----------------------------------------------------------------------===// // Miscellaneous Instructions. //===----------------------------------------------------------------------===// Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td +++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td @@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys "Assume that the miscellaneous-extensions facility is installed" >; +def FeatureTransactionalExecution : SystemZFeature< + "transactional-execution", "TransactionalExecution", + "Assume that the transactional-execution facility is installed" +>; + +def FeatureProcessorAssist : SystemZFeature< + "processor-assist", "ProcessorAssist", + "Assume that the processor-assist facility is installed" +>; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, @@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, FeatureFPExtension, FeaturePopulationCount, FeatureFastSerialization, FeatureInterlockedAccess1, - FeatureMiscellaneousExtensions]>; + FeatureMiscellaneousExtensions, + FeatureTransactionalExecution, FeatureProcessorAssist]>; Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), + HasTransactionalExecution(false), HasProcessorAssist(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h +++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h @@ -42,6 +42,8 @@ protected: bool HasFastSerialization; bool HasInterlockedAccess1; bool HasMiscellaneousExtensions; + bool HasTransactionalExecution; + bool HasProcessorAssist; private: Triple TargetTriple; @@ -102,6 +104,12 @@ public: return HasMiscellaneousExtensions; } + // Return true if the target has the transactional-execution facility. + bool hasTransactionalExecution() const { return HasTransactionalExecution; } + + // Return true if the target has the processor-assist facility. + bool hasProcessorAssist() const { return HasProcessorAssist; } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, Index: llvm-head/lib/Support/Triple.cpp =================================================================== --- llvm-head.orig/lib/Support/Triple.cpp +++ llvm-head/lib/Support/Triple.cpp @@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar case sparcv9: case sparc: return "sparc"; - case systemz: return "systemz"; + case systemz: return "s390"; case x86: case x86_64: return "x86"; Index: llvm-head/include/llvm/IR/Intrinsics.td =================================================================== --- llvm-head.orig/include/llvm/IR/Intrinsics.td +++ llvm-head/include/llvm/IR/Intrinsics.td @@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td" include "llvm/IR/IntrinsicsMips.td" include "llvm/IR/IntrinsicsR600.td" include "llvm/IR/IntrinsicsBPF.td" +include "llvm/IR/IntrinsicsSystemZ.td" Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td =================================================================== --- /dev/null +++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td @@ -0,0 +1,46 @@ +//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the SystemZ-specific intrinsics. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Transactional-execution intrinsics +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "s390" in { + def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty], + [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], + [IntrNoDuplicate]>; + + def int_s390_tabort : Intrinsic<[], [llvm_i64_ty], + [IntrNoReturn, Throws]>; + + def int_s390_tend : GCCBuiltin<"__builtin_tend">, + Intrinsic<[llvm_i32_ty], []>; + + def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">, + Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; + + def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty], + [IntrReadWriteArgMem]>; + + def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">, + Intrinsic<[], [llvm_i32_ty]>; +} + Index: llvm-head/lib/Target/SystemZ/SystemZ.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZ.h +++ llvm-head/lib/Target/SystemZ/SystemZ.h @@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0 = C const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3; const unsigned CCMASK_TM = CCMASK_ANY; +// Condition-code mask assignments for TRANSACTION_BEGIN. +const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0; +const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1; +const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2; +const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3; +const unsigned CCMASK_TBEGIN = CCMASK_ANY; + +// Condition-code mask assignments for TRANSACTION_END. +const unsigned CCMASK_TEND_TX = CCMASK_0; +const unsigned CCMASK_TEND_NOTX = CCMASK_2; +const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX; + // The position of the low CC bit in an IPM result. const unsigned IPM_CC = 28; Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h @@ -146,6 +146,15 @@ enum { // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) SERIALIZE, + // Transaction begin. The first operand is the chain, the second + // the TDB pointer, and the third the immediate control field. + // Returns chain and glue. + TBEGIN, + TBEGIN_NOFLOAT, + + // Transaction end. Just the chain operand. Returns chain and glue. + TEND, + // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or // ATOMIC_LOAD_<op>. // @@ -318,6 +327,7 @@ private: SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; // If the last instruction before MBBI in MBB was some form of COMPARE, // try to replace it with a COMPARE AND BRANCH just before MBBI. @@ -355,6 +365,10 @@ private: MachineBasicBlock *emitStringWrapper(MachineInstr *MI, MachineBasicBlock *BB, unsigned Opcode) const; + MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const; }; } // end namespace llvm Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp +++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/IR/Intrinsics.h" #include <cctype> using namespace llvm; @@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe // Codes for which we want to perform some z-specific combinations. setTargetDAGCombine(ISD::SIGN_EXTEND); + // Handle intrinsics. + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); + // We want to use MVC in preference to even a single load/store pair. MaxStoresPerMemcpy = 0; MaxStoresPerMemcpyOptSize = 0; @@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain); } +// Return true if Op is an intrinsic node with chain that returns the CC value +// as its only (other) argument. Provide the associated SystemZISD opcode and +// the mask of valid CC values if so. +static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode, + unsigned &CCValid) { + unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); + switch (Id) { + case Intrinsic::s390_tbegin: + Opcode = SystemZISD::TBEGIN; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tbegin_nofloat: + Opcode = SystemZISD::TBEGIN_NOFLOAT; + CCValid = SystemZ::CCMASK_TBEGIN; + return true; + + case Intrinsic::s390_tend: + Opcode = SystemZISD::TEND; + CCValid = SystemZ::CCMASK_TEND; + return true; + + default: + return false; + } +} + +// Emit an intrinsic with chain with a glued value instead of its CC result. +static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op, + unsigned Opcode) { + // Copy all operands except the intrinsic ID. + unsigned NumOps = Op.getNumOperands(); + SmallVector<SDValue, 6> Ops; + Ops.reserve(NumOps - 1); + Ops.push_back(Op.getOperand(0)); + for (unsigned I = 2; I < NumOps; ++I) + Ops.push_back(Op.getOperand(I)); + + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue); + SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops); + SDValue OldChain = SDValue(Op.getNode(), 1); + SDValue NewChain = SDValue(Intr.getNode(), 0); + DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain); + return Intr; +} + // CC is a comparison that will be implemented using an integer or // floating-point comparison. Return the condition code mask for // a branch on true. In the integer case, CCMASK_CMP_UO is set for @@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec C.CCMask = NewCCMask; } +// Return a Comparison that tests the condition-code result of intrinsic +// node Call against constant integer CC using comparison code Cond. +// Opcode is the opcode of the SystemZISD operation for the intrinsic +// and CCValid is the set of possible condition-code results. +static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, + SDValue Call, unsigned CCValid, uint64_t CC, + ISD::CondCode Cond) { + Comparison C(Call, SDValue()); + C.Opcode = Opcode; + C.CCValid = CCValid; + if (Cond == ISD::SETEQ) + // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3. + C.CCMask = CC < 4 ? 1 << (3 - CC) : 0; + else if (Cond == ISD::SETNE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1; + else if (Cond == ISD::SETLT || Cond == ISD::SETULT) + // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3, + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (4 - CC) : -1; + else if (Cond == ISD::SETGE || Cond == ISD::SETUGE) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0; + else if (Cond == ISD::SETLE || Cond == ISD::SETULE) + // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true), + // always true for CC>3. + C.CCMask = CC < 4 ? -1 << (3 - CC) : -1; + else if (Cond == ISD::SETGT || Cond == ISD::SETUGT) + // ...and the inverse of that. + C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0; + else + llvm_unreachable("Unexpected integer comparison type"); + C.CCMask &= CCValid; + return C; +} + // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1. static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond) { + if (CmpOp1.getOpcode() == ISD::Constant) { + uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue(); + unsigned Opcode, CCValid; + if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN && + CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) && + isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid)) + return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond); + } Comparison C(CmpOp0, CmpOp1); C.CCMask = CCMaskForCondCode(Cond); if (C.Op0.getValueType().isFloatingPoint()) { @@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D // Emit the comparison instruction described by C. static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) { + if (!C.Op1.getNode()) { + SDValue Op; + switch (C.Op0.getOpcode()) { + case ISD::INTRINSIC_W_CHAIN: + Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode); + break; + default: + llvm_unreachable("Invalid comparison operands"); + } + return SDValue(Op.getNode(), Op->getNumValues() - 1); + } if (C.Opcode == SystemZISD::ICMP) return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1, DAG.getConstant(C.ICmpType, MVT::i32)); @@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC } SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); SDValue CmpOp0 = Op.getOperand(2); SDValue CmpOp1 = Op.getOperand(3); @@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC)); SDValue Glue = emitCmp(DAG, DL, C); return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(), - Chain, DAG.getConstant(C.CCValid, MVT::i32), + Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32), DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue); } @@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF Node->getMemoryVT(), Node->getMemOperand()); } +// Return an i32 that contains the value of CC immediately after After, +// whose final operand must be MVT::Glue. +static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) { + SDValue Glue = SDValue(After, After->getNumValues() - 1); + SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue); + return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM, + DAG.getConstant(SystemZ::IPM_CC, MVT::i32)); +} + +SDValue +SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, + SelectionDAG &DAG) const { + unsigned Opcode, CCValid; + if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) { + assert(Op->getNumValues() == 2 && "Expected only CC result and chain"); + SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode); + SDValue CC = getCCResult(DAG, Glued.getNode()); + DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC); + return SDValue(); + } + + return SDValue(); +} + SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { @@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper return lowerSTACKRESTORE(Op, DAG); case ISD::PREFETCH: return lowerPREFETCH(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: + return lowerINTRINSIC_W_CHAIN(Op, DAG); default: llvm_unreachable("Unexpected node to lower"); } @@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa OPCODE(SEARCH_STRING); OPCODE(IPM); OPCODE(SERIALIZE); + OPCODE(TBEGIN); + OPCODE(TBEGIN_NOFLOAT); + OPCODE(TEND); OPCODE(ATOMIC_SWAPW); OPCODE(ATOMIC_LOADW_ADD); OPCODE(ATOMIC_LOADW_SUB); @@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper return DoneMBB; } +// Update TBEGIN instruction with final opcode and register clobbers. +MachineBasicBlock * +SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI, + MachineBasicBlock *MBB, + unsigned Opcode, + bool NoFloat) const { + MachineFunction &MF = *MBB->getParent(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + const SystemZInstrInfo *TII = Subtarget.getInstrInfo(); + + // Update opcode. + MI->setDesc(TII->get(Opcode)); + + // We cannot handle a TBEGIN that clobbers the stack or frame pointer. + // Make sure to add the corresponding GRSM bits if they are missing. + uint64_t Control = MI->getOperand(2).getImm(); + static const unsigned GPRControlBit[16] = { + 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000, + 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100 + }; + Control |= GPRControlBit[15]; + if (TFI->hasFP(MF)) + Control |= GPRControlBit[11]; + MI->getOperand(2).setImm(Control); + + // Add GPR clobbers. + for (int I = 0; I < 16; I++) { + if ((Control & GPRControlBit[I]) == 0) { + unsigned Reg = SystemZMC::GR64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + // Add FPR clobbers. + if (!NoFloat && (Control & 4) != 0) { + for (int I = 0; I < 16; I++) { + unsigned Reg = SystemZMC::FP64Regs[I]; + MI->addOperand(MachineOperand::CreateReg(Reg, true, true)); + } + } + + return MBB; +} + MachineBasicBlock *SystemZTargetLowering:: EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const { switch (MI->getOpcode()) { @@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr return emitStringWrapper(MI, MBB, SystemZ::MVST); case SystemZ::SRSTLoop: return emitStringWrapper(MI, MBB, SystemZ::SRST); + case SystemZ::TBEGIN: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false); + case SystemZ::TBEGIN_nofloat: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true); + case SystemZ::TBEGINC: + return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true); default: llvm_unreachable("Unexpected instr type to insert"); } Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll =================================================================== --- /dev/null +++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -0,0 +1,352 @@ +; Test transactional-execution intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +declare i32 @llvm.s390.tbegin(i8 *, i32) +declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) +declare void @llvm.s390.tbeginc(i8 *, i32) +declare i32 @llvm.s390.tend() +declare void @llvm.s390.tabort(i64) +declare void @llvm.s390.ntstg(i64, i64 *) +declare i32 @llvm.s390.etnd() +declare void @llvm.s390.ppa.txassist(i32) + +; TBEGIN. +define void @test_tbegin() { +; CHECK-LABEL: test_tbegin: +; CHECK-NOT: stmg +; CHECK: std %f8, +; CHECK: std %f9, +; CHECK: std %f10, +; CHECK: std %f11, +; CHECK: std %f12, +; CHECK: std %f13, +; CHECK: std %f14, +; CHECK: std %f15, +; CHECK: tbegin 0, 65292 +; CHECK: ld %f8, +; CHECK: ld %f9, +; CHECK: ld %f10, +; CHECK: ld %f11, +; CHECK: ld %f12, +; CHECK: ld %f13, +; CHECK: ld %f14, +; CHECK: ld %f15, +; CHECK: br %r14 + call i32 @llvm.s390.tbegin(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat). +define void @test_tbegin_nofloat1() { +; CHECK-LABEL: test_tbegin_nofloat1: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat) with integer CC return value. +define i32 @test_tbegin_nofloat2() { +; CHECK-LABEL: test_tbegin_nofloat2: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret i32 %res +} + +; TBEGIN (nofloat) with implicit CC check. +define void @test_tbegin_nofloat3(i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat3: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: jnh {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TBEGIN (nofloat) with dual CC use. +define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat4: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TBEGIN (nofloat) with register. +define void @test_tbegin_nofloat5(i8 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat5: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0(%r2), 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292) + ret void +} + +; TBEGIN (nofloat) with GRSM 0x0f00. +define void @test_tbegin_nofloat6() { +; CHECK-LABEL: test_tbegin_nofloat6: +; CHECK: stmg %r6, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 3840 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xf100. +define void @test_tbegin_nofloat7() { +; CHECK-LABEL: test_tbegin_nofloat7: +; CHECK: stmg %r8, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 61696 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically. +define void @test_tbegin_nofloat8() { +; CHECK-LABEL: test_tbegin_nofloat8: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed. +define void @test_tbegin_nofloat9() { +; CHECK-LABEL: test_tbegin_nofloat9: +; CHECK: stmg %r10, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 64256 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically. +define void @test_tbegin_nofloat10(i64 %n) { +; CHECK-LABEL: test_tbegin_nofloat10: +; CHECK: stmg %r11, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + %buf = alloca i8, i64 %n + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGINC. +define void @test_tbeginc() { +; CHECK-LABEL: test_tbeginc: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbeginc 0, 65288 +; CHECK: br %r14 + call void @llvm.s390.tbeginc(i8 *null, i32 65288) + ret void +} + +; TEND with integer CC return value. +define i32 @test_tend1() { +; CHECK-LABEL: test_tend1: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + ret i32 %res +} + +; TEND with implicit CC check. +define void @test_tend3(i32 *%ptr) { +; CHECK-LABEL: test_tend3: +; CHECK: tend +; CHECK: je {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TEND with dual CC use. +define i32 @test_tend2(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tend2: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TABORT with register only. +define void @test_tabort1(i64 %val) { +; CHECK-LABEL: test_tabort1: +; CHECK: tabort 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 %val) + ret void +} + +; TABORT with immediate only. +define void @test_tabort2(i64 %val) { +; CHECK-LABEL: test_tabort2: +; CHECK: tabort 1234 +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 1234) + ret void +} + +; TABORT with register + immediate. +define void @test_tabort3(i64 %val) { +; CHECK-LABEL: test_tabort3: +; CHECK: tabort 1234(%r2) +; CHECK: br %r14 + %sum = add i64 %val, 1234 + call void @llvm.s390.tabort(i64 %sum) + ret void +} + +; TABORT with out-of-range immediate. +define void @test_tabort4(i64 %val) { +; CHECK-LABEL: test_tabort4: +; CHECK: tabort 0({{%r[1-5]}}) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 4096) + ret void +} + +; NTSTG with base pointer only. +define void @test_ntstg1(i64 *%ptr, i64 %val) { +; CHECK-LABEL: test_ntstg1: +; CHECK: ntstg %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with base and index. +; Check that VSTL doesn't allow an index. +define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) { +; CHECK-LABEL: test_ntstg2: +; CHECK: sllg [[REG:%r[1-5]]], %r3, 3 +; CHECK: ntstg %r4, 0([[REG]],%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 %index + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the highest in-range displacement. +define void @test_ntstg3(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg3: +; CHECK: ntstg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65535 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range positive displacement. +define void @test_ntstg4(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg4: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the lowest in-range displacement. +define void @test_ntstg5(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg5: +; CHECK: ntstg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range negative displacement. +define void @test_ntstg6(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg6: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65537 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; ETND. +define i32 @test_etnd() { +; CHECK-LABEL: test_etnd: +; CHECK: etnd %r2 +; CHECK: br %r14 + %res = call i32 @llvm.s390.etnd() + ret i32 %res +} + +; PPA (Transaction-Abort Assist) +define void @test_ppa_txassist(i32 %val) { +; CHECK-LABEL: test_ppa_txassist: +; CHECK: ppa %r2, 0, 1 +; CHECK: br %r14 + call void @llvm.s390.ppa.txassist(i32 %val) + ret void +} + Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s @@ -3,6 +3,22 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: ntstg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ntstg %r0, 524288 + + ntstg %r0, -524289 + ntstg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: ppa %r0, %r0, 16 + + ppa %r0, %r0, -1 + ppa %r0, %r0, 16 + +#CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbgn %r0,%r0,0,0,64 @@ -22,3 +38,47 @@ risbgn %r0,%r0,-1,0,0 risbgn %r0,%r0,256,0,0 +#CHECK: error: invalid operand +#CHECK: tabort -1 +#CHECK: error: invalid operand +#CHECK: tabort 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: tabort 0(%r1,%r2) + + tabort -1 + tabort 4096 + tabort 0(%r1,%r2) + +#CHECK: error: invalid operand +#CHECK: tbegin -1, 0 +#CHECK: error: invalid operand +#CHECK: tbegin 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbegin 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbegin 0, -1 +#CHECK: error: invalid operand +#CHECK: tbegin 0, 65536 + + tbegin -1, 0 + tbegin 4096, 0 + tbegin 0(%r1,%r2), 0 + tbegin 0, -1 + tbegin 0, 65536 + +#CHECK: error: invalid operand +#CHECK: tbeginc -1, 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: tbeginc 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, -1 +#CHECK: error: invalid operand +#CHECK: tbeginc 0, 65536 + + tbeginc -1, 0 + tbeginc 4096, 0 + tbeginc 0(%r1,%r2), 0 + tbeginc 0, -1 + tbeginc 0, 65536 Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s +++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s @@ -1,6 +1,48 @@ # For zEC12 and above. # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s +#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00] +#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0] +#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70] + + etnd %r0 + etnd %r15 + etnd %r7 + +#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25] +#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25] +#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25] +#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25] +#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25] +#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25] +#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25] +#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25] +#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25] + + ntstg %r0, -524288 + ntstg %r0, -1 + ntstg %r0, 0 + ntstg %r0, 1 + ntstg %r0, 524287 + ntstg %r0, 0(%r1) + ntstg %r0, 0(%r15) + ntstg %r0, 524287(%r1,%r15) + ntstg %r0, 524287(%r15,%r1) + ntstg %r15, 0 + +#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00] +#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00] +#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f] +#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46] +#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0] + + ppa %r0, %r0, 0 + ppa %r0, %r0, 15 + ppa %r0, %r15, 0 + ppa %r4, %r6, 7 + ppa %r15, %r0, 0 + #CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] #CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] @@ -17,3 +59,68 @@ risbgn %r15,%r0,0,0,0 risbgn %r4,%r5,6,7,8 +#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00] +#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00] +#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00] +#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff] +#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff] +#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff] + + tabort 0 + tabort 0(%r1) + tabort 0(%r15) + tabort 4095 + tabort 4095(%r1) + tabort 4095(%r15) + +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00] +#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00] +#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01] +#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff] +#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00] +#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff] +#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a] +#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a] +#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a] +#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a] + + tbegin 0, 0 + tbegin 4095, 0 + tbegin 0, 0 + tbegin 0, 1 + tbegin 0, 32767 + tbegin 0, 32768 + tbegin 0, 65535 + tbegin 0(%r1), 42 + tbegin 0(%r15), 42 + tbegin 4095(%r1), 42 + tbegin 4095(%r15), 42 + +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00] +#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00] +#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01] +#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff] +#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00] +#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff] +#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a] +#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a] +#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a] +#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a] + + tbeginc 0, 0 + tbeginc 4095, 0 + tbeginc 0, 0 + tbeginc 0, 1 + tbeginc 0, 32767 + tbeginc 0, 32768 + tbeginc 0, 65535 + tbeginc 0(%r1), 42 + tbeginc 0(%r15), 42 + tbeginc 4095(%r1), 42 + tbeginc 4095(%r15), 42 + +#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00] + + tend Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s =================================================================== --- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s +++ llvm-head/test/MC/SystemZ/insn-bad-z196.s @@ -244,6 +244,11 @@ cxlgbr %f0, 16, %r0, 0 cxlgbr %f2, 0, %r0, 0 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: etnd %r7 + + etnd %r7 + #CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, -1 #CHECK: error: invalid operand @@ -546,6 +551,16 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: ntstg %r0, 524287(%r1,%r15) + + ntstg %r0, 524287(%r1,%r15) + +#CHECK: error: {{(instruction requires: processor-assist)?}} +#CHECK: ppa %r4, %r6, 7 + + ppa %r4, %r6, 7 + #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}} #CHECK: risbgn %r1, %r2, 0, 0, 0 @@ -690,3 +705,24 @@ stocg %r0,-524289,1 stocg %r0,524288,1 stocg %r0,0(%r1,%r2),1 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tabort 4095(%r1) + + tabort 4095(%r1) + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbegin 4095(%r1), 42 + + tbegin 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tbeginc 4095(%r1), 42 + + tbeginc 4095(%r1), 42 + +#CHECK: error: {{(instruction requires: transactional-execution)?}} +#CHECK: tend + + tend + Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt +++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt @@ -2503,6 +2503,15 @@ # CHECK: ear %r15, %a15 0xb2 0x4f 0x00 0xff +# CHECK: etnd %r0 +0xb2 0xec 0x00 0x00 + +# CHECK: etnd %r15 +0xb2 0xec 0x00 0xf0 + +# CHECK: etnd %r7 +0xb2 0xec 0x00 0x70 + # CHECK: fidbr %f0, 0, %f0 0xb3 0x5f 0x00 0x00 @@ -6034,6 +6043,36 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: ntstg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x25 + +# CHECK: ntstg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x25 + +# CHECK: ntstg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x25 + +# CHECK: ntstg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: ntstg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x25 + +# CHECK: ntstg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x25 + +# CHECK: ntstg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x25 + # CHECK: oc 0(1), 0 0xd6 0x00 0x00 0x00 0x00 0x00 @@ -6346,6 +6385,21 @@ # CHECK: popcnt %r7, %r8 0xb9 0xe1 0x00 0x78 +# CHECK: ppa %r0, %r0, 0 +0xb2 0xe8 0x00 0x00 + +# CHECK: ppa %r0, %r0, 15 +0xb2 0xe8 0xf0 0x00 + +# CHECK: ppa %r0, %r15, 0 +0xb2 0xe8 0x00 0x0f + +# CHECK: ppa %r4, %r6, 7 +0xb2 0xe8 0x70 0x46 + +# CHECK: ppa %r15, %r0, 0 +0xb2 0xe8 0x00 0xf0 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -8062,6 +8116,93 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tabort 0 +0xb2 0xfc 0x00 0x00 + +# CHECK: tabort 0(%r1) +0xb2 0xfc 0x10 0x00 + +# CHECK: tabort 0(%r15) +0xb2 0xfc 0xf0 0x00 + +# CHECK: tabort 4095 +0xb2 0xfc 0x0f 0xff + +# CHECK: tabort 4095(%r1) +0xb2 0xfc 0x1f 0xff + +# CHECK: tabort 4095(%r15) +0xb2 0xfc 0xff 0xff + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 4095, 0 +0xe5 0x60 0x0f 0xff 0x00 0x00 + +# CHECK: tbegin 0, 0 +0xe5 0x60 0x00 0x00 0x00 0x00 + +# CHECK: tbegin 0, 1 +0xe5 0x60 0x00 0x00 0x00 0x01 + +# CHECK: tbegin 0, 32767 +0xe5 0x60 0x00 0x00 0x7f 0xff + +# CHECK: tbegin 0, 32768 +0xe5 0x60 0x00 0x00 0x80 0x00 + +# CHECK: tbegin 0, 65535 +0xe5 0x60 0x00 0x00 0xff 0xff + +# CHECK: tbegin 0(%r1), 42 +0xe5 0x60 0x10 0x00 0x00 0x2a + +# CHECK: tbegin 0(%r15), 42 +0xe5 0x60 0xf0 0x00 0x00 0x2a + +# CHECK: tbegin 4095(%r1), 42 +0xe5 0x60 0x1f 0xff 0x00 0x2a + +# CHECK: tbegin 4095(%r15), 42 +0xe5 0x60 0xff 0xff 0x00 0x2a + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 4095, 0 +0xe5 0x61 0x0f 0xff 0x00 0x00 + +# CHECK: tbeginc 0, 0 +0xe5 0x61 0x00 0x00 0x00 0x00 + +# CHECK: tbeginc 0, 1 +0xe5 0x61 0x00 0x00 0x00 0x01 + +# CHECK: tbeginc 0, 32767 +0xe5 0x61 0x00 0x00 0x7f 0xff + +# CHECK: tbeginc 0, 32768 +0xe5 0x61 0x00 0x00 0x80 0x00 + +# CHECK: tbeginc 0, 65535 +0xe5 0x61 0x00 0x00 0xff 0xff + +# CHECK: tbeginc 0(%r1), 42 +0xe5 0x61 0x10 0x00 0x00 0x2a + +# CHECK: tbeginc 0(%r15), 42 +0xe5 0x61 0xf0 0x00 0x00 0x2a + +# CHECK: tbeginc 4095(%r1), 42 +0xe5 0x61 0x1f 0xff 0x00 0x2a + +# CHECK: tbeginc 4095(%r15), 42 +0xe5 0x61 0xff 0xff 0x00 0x2a + +# CHECK: tend +0xb2 0xf8 0x00 0x00 + # CHECK: tm 0, 0 0x91 0x00 0x00 0x00 llvm-svn: 233803
·
llvmorg-21-initllvmorg-3.7.0-rc1
1 parent 8db9e77 commit 57c85f5

17 files changed

+1054
-4
lines changed
 

‎llvm/include/llvm/IR/Intrinsics.td

+1
Original file line numberDiff line numberDiff line change
@@ -630,3 +630,4 @@ include "llvm/IR/IntrinsicsNVVM.td"
630630
include "llvm/IR/IntrinsicsMips.td"
631631
include "llvm/IR/IntrinsicsR600.td"
632632
include "llvm/IR/IntrinsicsBPF.td"
633+
include "llvm/IR/IntrinsicsSystemZ.td"

‎llvm/include/llvm/IR/IntrinsicsSystemZ.td

+46
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===//
2+
//
3+
// The LLVM Compiler Infrastructure
4+
//
5+
// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
7+
//
8+
//===----------------------------------------------------------------------===//
9+
//
10+
// This file defines all of the SystemZ-specific intrinsics.
11+
//
12+
//===----------------------------------------------------------------------===//
13+
14+
//===----------------------------------------------------------------------===//
15+
//
16+
// Transactional-execution intrinsics
17+
//
18+
//===----------------------------------------------------------------------===//
19+
20+
let TargetPrefix = "s390" in {
21+
def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
22+
[IntrNoDuplicate]>;
23+
24+
def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
25+
[llvm_ptr_ty, llvm_i32_ty],
26+
[IntrNoDuplicate]>;
27+
28+
def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
29+
[IntrNoDuplicate]>;
30+
31+
def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
32+
[IntrNoReturn, Throws]>;
33+
34+
def int_s390_tend : GCCBuiltin<"__builtin_tend">,
35+
Intrinsic<[llvm_i32_ty], []>;
36+
37+
def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
38+
Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
39+
40+
def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
41+
[IntrReadWriteArgMem]>;
42+
43+
def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
44+
Intrinsic<[], [llvm_i32_ty]>;
45+
}
46+

‎llvm/lib/Support/Triple.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
9292
case sparcv9:
9393
case sparc: return "sparc";
9494

95-
case systemz: return "systemz";
95+
case systemz: return "s390";
9696

9797
case x86:
9898
case x86_64: return "x86";

‎llvm/lib/Target/SystemZ/SystemZ.h

+12
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0 = CCMASK_0 | CCMASK_1;
6868
const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3;
6969
const unsigned CCMASK_TM = CCMASK_ANY;
7070

71+
// Condition-code mask assignments for TRANSACTION_BEGIN.
72+
const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0;
73+
const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
74+
const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2;
75+
const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3;
76+
const unsigned CCMASK_TBEGIN = CCMASK_ANY;
77+
78+
// Condition-code mask assignments for TRANSACTION_END.
79+
const unsigned CCMASK_TEND_TX = CCMASK_0;
80+
const unsigned CCMASK_TEND_NOTX = CCMASK_2;
81+
const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
82+
7183
// The position of the low CC bit in an IPM result.
7284
const unsigned IPM_CC = 28;
7385

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

+186-2
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "llvm/CodeGen/MachineInstrBuilder.h"
2121
#include "llvm/CodeGen/MachineRegisterInfo.h"
2222
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23+
#include "llvm/IR/Intrinsics.h"
2324
#include <cctype>
2425

2526
using namespace llvm;
@@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
304305
// Codes for which we want to perform some z-specific combinations.
305306
setTargetDAGCombine(ISD::SIGN_EXTEND);
306307

308+
// Handle intrinsics.
309+
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
310+
307311
// We want to use MVC in preference to even a single load/store pair.
308312
MaxStoresPerMemcpy = 0;
309313
MaxStoresPerMemcpyOptSize = 0;
@@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
10311035
return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
10321036
}
10331037

1038+
// Return true if Op is an intrinsic node with chain that returns the CC value
1039+
// as its only (other) argument. Provide the associated SystemZISD opcode and
1040+
// the mask of valid CC values if so.
1041+
static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1042+
unsigned &CCValid) {
1043+
unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1044+
switch (Id) {
1045+
case Intrinsic::s390_tbegin:
1046+
Opcode = SystemZISD::TBEGIN;
1047+
CCValid = SystemZ::CCMASK_TBEGIN;
1048+
return true;
1049+
1050+
case Intrinsic::s390_tbegin_nofloat:
1051+
Opcode = SystemZISD::TBEGIN_NOFLOAT;
1052+
CCValid = SystemZ::CCMASK_TBEGIN;
1053+
return true;
1054+
1055+
case Intrinsic::s390_tend:
1056+
Opcode = SystemZISD::TEND;
1057+
CCValid = SystemZ::CCMASK_TEND;
1058+
return true;
1059+
1060+
default:
1061+
return false;
1062+
}
1063+
}
1064+
1065+
// Emit an intrinsic with chain with a glued value instead of its CC result.
1066+
static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1067+
unsigned Opcode) {
1068+
// Copy all operands except the intrinsic ID.
1069+
unsigned NumOps = Op.getNumOperands();
1070+
SmallVector<SDValue, 6> Ops;
1071+
Ops.reserve(NumOps - 1);
1072+
Ops.push_back(Op.getOperand(0));
1073+
for (unsigned I = 2; I < NumOps; ++I)
1074+
Ops.push_back(Op.getOperand(I));
1075+
1076+
assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1077+
SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1078+
SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1079+
SDValue OldChain = SDValue(Op.getNode(), 1);
1080+
SDValue NewChain = SDValue(Intr.getNode(), 0);
1081+
DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1082+
return Intr;
1083+
}
1084+
10341085
// CC is a comparison that will be implemented using an integer or
10351086
// floating-point comparison. Return the condition code mask for
10361087
// a branch on true. In the integer case, CCMASK_CMP_UO is set for
@@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
15881639
C.CCMask = NewCCMask;
15891640
}
15901641

1642+
// Return a Comparison that tests the condition-code result of intrinsic
1643+
// node Call against constant integer CC using comparison code Cond.
1644+
// Opcode is the opcode of the SystemZISD operation for the intrinsic
1645+
// and CCValid is the set of possible condition-code results.
1646+
static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
1647+
SDValue Call, unsigned CCValid, uint64_t CC,
1648+
ISD::CondCode Cond) {
1649+
Comparison C(Call, SDValue());
1650+
C.Opcode = Opcode;
1651+
C.CCValid = CCValid;
1652+
if (Cond == ISD::SETEQ)
1653+
// bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
1654+
C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
1655+
else if (Cond == ISD::SETNE)
1656+
// ...and the inverse of that.
1657+
C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
1658+
else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
1659+
// bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
1660+
// always true for CC>3.
1661+
C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
1662+
else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
1663+
// ...and the inverse of that.
1664+
C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
1665+
else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
1666+
// bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
1667+
// always true for CC>3.
1668+
C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
1669+
else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
1670+
// ...and the inverse of that.
1671+
C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
1672+
else
1673+
llvm_unreachable("Unexpected integer comparison type");
1674+
C.CCMask &= CCValid;
1675+
return C;
1676+
}
1677+
15911678
// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
15921679
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
15931680
ISD::CondCode Cond) {
1681+
if (CmpOp1.getOpcode() == ISD::Constant) {
1682+
uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
1683+
unsigned Opcode, CCValid;
1684+
if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
1685+
CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
1686+
isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
1687+
return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
1688+
}
15941689
Comparison C(CmpOp0, CmpOp1);
15951690
C.CCMask = CCMaskForCondCode(Cond);
15961691
if (C.Op0.getValueType().isFloatingPoint()) {
@@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
16321727

16331728
// Emit the comparison instruction described by C.
16341729
static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1730+
if (!C.Op1.getNode()) {
1731+
SDValue Op;
1732+
switch (C.Op0.getOpcode()) {
1733+
case ISD::INTRINSIC_W_CHAIN:
1734+
Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
1735+
break;
1736+
default:
1737+
llvm_unreachable("Invalid comparison operands");
1738+
}
1739+
return SDValue(Op.getNode(), Op->getNumValues() - 1);
1740+
}
16351741
if (C.Opcode == SystemZISD::ICMP)
16361742
return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
16371743
DAG.getConstant(C.ICmpType, MVT::i32));
@@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
17131819
}
17141820

17151821
SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1716-
SDValue Chain = Op.getOperand(0);
17171822
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
17181823
SDValue CmpOp0 = Op.getOperand(2);
17191824
SDValue CmpOp1 = Op.getOperand(3);
@@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
17231828
Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
17241829
SDValue Glue = emitCmp(DAG, DL, C);
17251830
return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1726-
Chain, DAG.getConstant(C.CCValid, MVT::i32),
1831+
Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
17271832
DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
17281833
}
17291834

@@ -2562,6 +2667,30 @@ SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
25622667
Node->getMemoryVT(), Node->getMemOperand());
25632668
}
25642669

2670+
// Return an i32 that contains the value of CC immediately after After,
2671+
// whose final operand must be MVT::Glue.
2672+
static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
2673+
SDValue Glue = SDValue(After, After->getNumValues() - 1);
2674+
SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
2675+
return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
2676+
DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
2677+
}
2678+
2679+
SDValue
2680+
SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2681+
SelectionDAG &DAG) const {
2682+
unsigned Opcode, CCValid;
2683+
if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
2684+
assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
2685+
SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
2686+
SDValue CC = getCCResult(DAG, Glued.getNode());
2687+
DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
2688+
return SDValue();
2689+
}
2690+
2691+
return SDValue();
2692+
}
2693+
25652694
SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
25662695
SelectionDAG &DAG) const {
25672696
switch (Op.getOpcode()) {
@@ -2635,6 +2764,8 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
26352764
return lowerSTACKRESTORE(Op, DAG);
26362765
case ISD::PREFETCH:
26372766
return lowerPREFETCH(Op, DAG);
2767+
case ISD::INTRINSIC_W_CHAIN:
2768+
return lowerINTRINSIC_W_CHAIN(Op, DAG);
26382769
default:
26392770
llvm_unreachable("Unexpected node to lower");
26402771
}
@@ -2675,6 +2806,9 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
26752806
OPCODE(SEARCH_STRING);
26762807
OPCODE(IPM);
26772808
OPCODE(SERIALIZE);
2809+
OPCODE(TBEGIN);
2810+
OPCODE(TBEGIN_NOFLOAT);
2811+
OPCODE(TEND);
26782812
OPCODE(ATOMIC_SWAPW);
26792813
OPCODE(ATOMIC_LOADW_ADD);
26802814
OPCODE(ATOMIC_LOADW_SUB);
@@ -3502,6 +3636,50 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
35023636
return DoneMBB;
35033637
}
35043638

3639+
// Update TBEGIN instruction with final opcode and register clobbers.
3640+
MachineBasicBlock *
3641+
SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
3642+
MachineBasicBlock *MBB,
3643+
unsigned Opcode,
3644+
bool NoFloat) const {
3645+
MachineFunction &MF = *MBB->getParent();
3646+
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
3647+
const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
3648+
3649+
// Update opcode.
3650+
MI->setDesc(TII->get(Opcode));
3651+
3652+
// We cannot handle a TBEGIN that clobbers the stack or frame pointer.
3653+
// Make sure to add the corresponding GRSM bits if they are missing.
3654+
uint64_t Control = MI->getOperand(2).getImm();
3655+
static const unsigned GPRControlBit[16] = {
3656+
0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
3657+
0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
3658+
};
3659+
Control |= GPRControlBit[15];
3660+
if (TFI->hasFP(MF))
3661+
Control |= GPRControlBit[11];
3662+
MI->getOperand(2).setImm(Control);
3663+
3664+
// Add GPR clobbers.
3665+
for (int I = 0; I < 16; I++) {
3666+
if ((Control & GPRControlBit[I]) == 0) {
3667+
unsigned Reg = SystemZMC::GR64Regs[I];
3668+
MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
3669+
}
3670+
}
3671+
3672+
// Add FPR clobbers.
3673+
if (!NoFloat && (Control & 4) != 0) {
3674+
for (int I = 0; I < 16; I++) {
3675+
unsigned Reg = SystemZMC::FP64Regs[I];
3676+
MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
3677+
}
3678+
}
3679+
3680+
return MBB;
3681+
}
3682+
35053683
MachineBasicBlock *SystemZTargetLowering::
35063684
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
35073685
switch (MI->getOpcode()) {
@@ -3743,6 +3921,12 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
37433921
return emitStringWrapper(MI, MBB, SystemZ::MVST);
37443922
case SystemZ::SRSTLoop:
37453923
return emitStringWrapper(MI, MBB, SystemZ::SRST);
3924+
case SystemZ::TBEGIN:
3925+
return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
3926+
case SystemZ::TBEGIN_nofloat:
3927+
return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
3928+
case SystemZ::TBEGINC:
3929+
return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
37463930
default:
37473931
llvm_unreachable("Unexpected instr type to insert");
37483932
}

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

+14
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,15 @@ enum {
146146
// Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
147147
SERIALIZE,
148148

149+
// Transaction begin. The first operand is the chain, the second
150+
// the TDB pointer, and the third the immediate control field.
151+
// Returns chain and glue.
152+
TBEGIN,
153+
TBEGIN_NOFLOAT,
154+
155+
// Transaction end. Just the chain operand. Returns chain and glue.
156+
TEND,
157+
149158
// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
150159
// ATOMIC_LOAD_<op>.
151160
//
@@ -318,6 +327,7 @@ class SystemZTargetLowering : public TargetLowering {
318327
SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
319328
SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
320329
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
330+
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
321331

322332
// If the last instruction before MBBI in MBB was some form of COMPARE,
323333
// try to replace it with a COMPARE AND BRANCH just before MBBI.
@@ -355,6 +365,10 @@ class SystemZTargetLowering : public TargetLowering {
355365
MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
356366
MachineBasicBlock *BB,
357367
unsigned Opcode) const;
368+
MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
369+
MachineBasicBlock *MBB,
370+
unsigned Opcode,
371+
bool NoFloat) const;
358372
};
359373
} // end namespace llvm
360374

‎llvm/lib/Target/SystemZ/SystemZInstrFormats.td

+11
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
473473
let Inst{15-0} = BD2;
474474
}
475475

476+
class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
477+
: InstSystemZ<4, outs, ins, asmstr, pattern> {
478+
field bits<32> Inst;
479+
field bits<32> SoftFail = 0;
480+
481+
bits<16> BD2;
482+
483+
let Inst{31-16} = op;
484+
let Inst{15-0} = BD2;
485+
}
486+
476487
//===----------------------------------------------------------------------===//
477488
// Instruction definitions with semantics
478489
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.td

+54
Original file line numberDiff line numberDiff line change
@@ -1361,6 +1361,60 @@ let Defs = [CC] in {
13611361
def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
13621362
}
13631363

1364+
//===----------------------------------------------------------------------===//
1365+
// Transactional execution
1366+
//===----------------------------------------------------------------------===//
1367+
1368+
let Predicates = [FeatureTransactionalExecution] in {
1369+
// Transaction Begin
1370+
let hasSideEffects = 1, mayStore = 1,
1371+
usesCustomInserter = 1, Defs = [CC] in {
1372+
def TBEGIN : InstSIL<0xE560,
1373+
(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1374+
"tbegin\t$BD1, $I2",
1375+
[(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
1376+
def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1377+
[(z_tbegin_nofloat bdaddr12only:$BD1,
1378+
imm32zx16:$I2)]>;
1379+
def TBEGINC : InstSIL<0xE561,
1380+
(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1381+
"tbeginc\t$BD1, $I2",
1382+
[(int_s390_tbeginc bdaddr12only:$BD1,
1383+
imm32zx16:$I2)]>;
1384+
}
1385+
1386+
// Transaction End
1387+
let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
1388+
def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
1389+
1390+
// Transaction Abort
1391+
let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
1392+
def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
1393+
"tabort\t$BD2",
1394+
[(int_s390_tabort bdaddr12only:$BD2)]>;
1395+
1396+
// Nontransactional Store
1397+
let hasSideEffects = 1 in
1398+
def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
1399+
1400+
// Extract Transaction Nesting Depth
1401+
let hasSideEffects = 1 in
1402+
def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
1403+
}
1404+
1405+
//===----------------------------------------------------------------------===//
1406+
// Processor assist
1407+
//===----------------------------------------------------------------------===//
1408+
1409+
let Predicates = [FeatureProcessorAssist] in {
1410+
let hasSideEffects = 1, R4 = 0 in
1411+
def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
1412+
"ppa\t$R1, $R2, $R3", []>;
1413+
def : Pat<(int_s390_ppa_txassist GR32:$src),
1414+
(PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
1415+
0, 1)>;
1416+
}
1417+
13641418
//===----------------------------------------------------------------------===//
13651419
// Miscellaneous Instructions.
13661420
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/SystemZ/SystemZOperators.td

+12
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
7979
def SDT_ZPrefetch : SDTypeProfile<0, 2,
8080
[SDTCisVT<0, i32>,
8181
SDTCisPtrTy<1>]>;
82+
def SDT_ZTBegin : SDTypeProfile<0, 2,
83+
[SDTCisPtrTy<0>,
84+
SDTCisVT<1, i32>]>;
8285

8386
//===----------------------------------------------------------------------===//
8487
// Node definitions
@@ -180,6 +183,15 @@ def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
180183
[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
181184
SDNPMemOperand]>;
182185

186+
def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
187+
[SDNPHasChain, SDNPOutGlue, SDNPMayStore,
188+
SDNPSideEffect]>;
189+
def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
190+
[SDNPHasChain, SDNPOutGlue, SDNPMayStore,
191+
SDNPSideEffect]>;
192+
def z_tend : SDNode<"SystemZISD::TEND", SDTNone,
193+
[SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194+
183195
//===----------------------------------------------------------------------===//
184196
// Pattern fragments
185197
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/SystemZ/SystemZProcessors.td

+12-1
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : SystemZFeature<
6060
"Assume that the miscellaneous-extensions facility is installed"
6161
>;
6262

63+
def FeatureTransactionalExecution : SystemZFeature<
64+
"transactional-execution", "TransactionalExecution",
65+
"Assume that the transactional-execution facility is installed"
66+
>;
67+
68+
def FeatureProcessorAssist : SystemZFeature<
69+
"processor-assist", "ProcessorAssist",
70+
"Assume that the processor-assist facility is installed"
71+
>;
72+
6373
def : Processor<"generic", NoItineraries, []>;
6474
def : Processor<"z10", NoItineraries, []>;
6575
def : Processor<"z196", NoItineraries,
@@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
7080
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
7181
FeatureFPExtension, FeaturePopulationCount,
7282
FeatureFastSerialization, FeatureInterlockedAccess1,
73-
FeatureMiscellaneousExtensions]>;
83+
FeatureMiscellaneousExtensions,
84+
FeatureTransactionalExecution, FeatureProcessorAssist]>;

‎llvm/lib/Target/SystemZ/SystemZSubtarget.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
4040
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
4141
HasPopulationCount(false), HasFastSerialization(false),
4242
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
43+
HasTransactionalExecution(false), HasProcessorAssist(false),
4344
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
4445
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}
4546

‎llvm/lib/Target/SystemZ/SystemZSubtarget.h

+8
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,8 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
4242
bool HasFastSerialization;
4343
bool HasInterlockedAccess1;
4444
bool HasMiscellaneousExtensions;
45+
bool HasTransactionalExecution;
46+
bool HasProcessorAssist;
4547

4648
private:
4749
Triple TargetTriple;
@@ -102,6 +104,12 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
102104
return HasMiscellaneousExtensions;
103105
}
104106

107+
// Return true if the target has the transactional-execution facility.
108+
bool hasTransactionalExecution() const { return HasTransactionalExecution; }
109+
110+
// Return true if the target has the processor-assist facility.
111+
bool hasProcessorAssist() const { return HasProcessorAssist; }
112+
105113
// Return true if GV can be accessed using LARL for reloc model RM
106114
// and code model CM.
107115
bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,

‎llvm/test/CodeGen/SystemZ/htm-intrinsics.ll

+352
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,352 @@
1+
; Test transactional-execution intrinsics.
2+
;
3+
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
4+
5+
declare i32 @llvm.s390.tbegin(i8 *, i32)
6+
declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
7+
declare void @llvm.s390.tbeginc(i8 *, i32)
8+
declare i32 @llvm.s390.tend()
9+
declare void @llvm.s390.tabort(i64)
10+
declare void @llvm.s390.ntstg(i64, i64 *)
11+
declare i32 @llvm.s390.etnd()
12+
declare void @llvm.s390.ppa.txassist(i32)
13+
14+
; TBEGIN.
15+
define void @test_tbegin() {
16+
; CHECK-LABEL: test_tbegin:
17+
; CHECK-NOT: stmg
18+
; CHECK: std %f8,
19+
; CHECK: std %f9,
20+
; CHECK: std %f10,
21+
; CHECK: std %f11,
22+
; CHECK: std %f12,
23+
; CHECK: std %f13,
24+
; CHECK: std %f14,
25+
; CHECK: std %f15,
26+
; CHECK: tbegin 0, 65292
27+
; CHECK: ld %f8,
28+
; CHECK: ld %f9,
29+
; CHECK: ld %f10,
30+
; CHECK: ld %f11,
31+
; CHECK: ld %f12,
32+
; CHECK: ld %f13,
33+
; CHECK: ld %f14,
34+
; CHECK: ld %f15,
35+
; CHECK: br %r14
36+
call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
37+
ret void
38+
}
39+
40+
; TBEGIN (nofloat).
41+
define void @test_tbegin_nofloat1() {
42+
; CHECK-LABEL: test_tbegin_nofloat1:
43+
; CHECK-NOT: stmg
44+
; CHECK-NOT: std
45+
; CHECK: tbegin 0, 65292
46+
; CHECK: br %r14
47+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
48+
ret void
49+
}
50+
51+
; TBEGIN (nofloat) with integer CC return value.
52+
define i32 @test_tbegin_nofloat2() {
53+
; CHECK-LABEL: test_tbegin_nofloat2:
54+
; CHECK-NOT: stmg
55+
; CHECK-NOT: std
56+
; CHECK: tbegin 0, 65292
57+
; CHECK: ipm %r2
58+
; CHECK: srl %r2, 28
59+
; CHECK: br %r14
60+
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
61+
ret i32 %res
62+
}
63+
64+
; TBEGIN (nofloat) with implicit CC check.
65+
define void @test_tbegin_nofloat3(i32 *%ptr) {
66+
; CHECK-LABEL: test_tbegin_nofloat3:
67+
; CHECK-NOT: stmg
68+
; CHECK-NOT: std
69+
; CHECK: tbegin 0, 65292
70+
; CHECK: jnh {{\.L*}}
71+
; CHECK: mvhi 0(%r2), 0
72+
; CHECK: br %r14
73+
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
74+
%cmp = icmp eq i32 %res, 2
75+
br i1 %cmp, label %if.then, label %if.end
76+
77+
if.then: ; preds = %entry
78+
store i32 0, i32* %ptr, align 4
79+
br label %if.end
80+
81+
if.end: ; preds = %if.then, %entry
82+
ret void
83+
}
84+
85+
; TBEGIN (nofloat) with dual CC use.
86+
define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
87+
; CHECK-LABEL: test_tbegin_nofloat4:
88+
; CHECK-NOT: stmg
89+
; CHECK-NOT: std
90+
; CHECK: tbegin 0, 65292
91+
; CHECK: ipm %r2
92+
; CHECK: srl %r2, 28
93+
; CHECK: cijlh %r2, 2, {{\.L*}}
94+
; CHECK: mvhi 0(%r3), 0
95+
; CHECK: br %r14
96+
%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
97+
%cmp = icmp eq i32 %res, 2
98+
br i1 %cmp, label %if.then, label %if.end
99+
100+
if.then: ; preds = %entry
101+
store i32 0, i32* %ptr, align 4
102+
br label %if.end
103+
104+
if.end: ; preds = %if.then, %entry
105+
ret i32 %res
106+
}
107+
108+
; TBEGIN (nofloat) with register.
109+
define void @test_tbegin_nofloat5(i8 *%ptr) {
110+
; CHECK-LABEL: test_tbegin_nofloat5:
111+
; CHECK-NOT: stmg
112+
; CHECK-NOT: std
113+
; CHECK: tbegin 0(%r2), 65292
114+
; CHECK: br %r14
115+
call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
116+
ret void
117+
}
118+
119+
; TBEGIN (nofloat) with GRSM 0x0f00.
120+
define void @test_tbegin_nofloat6() {
121+
; CHECK-LABEL: test_tbegin_nofloat6:
122+
; CHECK: stmg %r6, %r15,
123+
; CHECK-NOT: std
124+
; CHECK: tbegin 0, 3840
125+
; CHECK: br %r14
126+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
127+
ret void
128+
}
129+
130+
; TBEGIN (nofloat) with GRSM 0xf100.
131+
define void @test_tbegin_nofloat7() {
132+
; CHECK-LABEL: test_tbegin_nofloat7:
133+
; CHECK: stmg %r8, %r15,
134+
; CHECK-NOT: std
135+
; CHECK: tbegin 0, 61696
136+
; CHECK: br %r14
137+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
138+
ret void
139+
}
140+
141+
; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
142+
define void @test_tbegin_nofloat8() {
143+
; CHECK-LABEL: test_tbegin_nofloat8:
144+
; CHECK-NOT: stmg
145+
; CHECK-NOT: std
146+
; CHECK: tbegin 0, 65280
147+
; CHECK: br %r14
148+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
149+
ret void
150+
}
151+
152+
; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
153+
define void @test_tbegin_nofloat9() {
154+
; CHECK-LABEL: test_tbegin_nofloat9:
155+
; CHECK: stmg %r10, %r15,
156+
; CHECK-NOT: std
157+
; CHECK: tbegin 0, 64256
158+
; CHECK: br %r14
159+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
160+
ret void
161+
}
162+
163+
; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
164+
define void @test_tbegin_nofloat10(i64 %n) {
165+
; CHECK-LABEL: test_tbegin_nofloat10:
166+
; CHECK: stmg %r11, %r15,
167+
; CHECK-NOT: std
168+
; CHECK: tbegin 0, 65280
169+
; CHECK: br %r14
170+
%buf = alloca i8, i64 %n
171+
call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
172+
ret void
173+
}
174+
175+
; TBEGINC.
176+
define void @test_tbeginc() {
177+
; CHECK-LABEL: test_tbeginc:
178+
; CHECK-NOT: stmg
179+
; CHECK-NOT: std
180+
; CHECK: tbeginc 0, 65288
181+
; CHECK: br %r14
182+
call void @llvm.s390.tbeginc(i8 *null, i32 65288)
183+
ret void
184+
}
185+
186+
; TEND with integer CC return value.
187+
define i32 @test_tend1() {
188+
; CHECK-LABEL: test_tend1:
189+
; CHECK: tend
190+
; CHECK: ipm %r2
191+
; CHECK: srl %r2, 28
192+
; CHECK: br %r14
193+
%res = call i32 @llvm.s390.tend()
194+
ret i32 %res
195+
}
196+
197+
; TEND with implicit CC check.
198+
define void @test_tend3(i32 *%ptr) {
199+
; CHECK-LABEL: test_tend3:
200+
; CHECK: tend
201+
; CHECK: je {{\.L*}}
202+
; CHECK: mvhi 0(%r2), 0
203+
; CHECK: br %r14
204+
%res = call i32 @llvm.s390.tend()
205+
%cmp = icmp eq i32 %res, 2
206+
br i1 %cmp, label %if.then, label %if.end
207+
208+
if.then: ; preds = %entry
209+
store i32 0, i32* %ptr, align 4
210+
br label %if.end
211+
212+
if.end: ; preds = %if.then, %entry
213+
ret void
214+
}
215+
216+
; TEND with dual CC use.
217+
define i32 @test_tend2(i32 %pad, i32 *%ptr) {
218+
; CHECK-LABEL: test_tend2:
219+
; CHECK: tend
220+
; CHECK: ipm %r2
221+
; CHECK: srl %r2, 28
222+
; CHECK: cijlh %r2, 2, {{\.L*}}
223+
; CHECK: mvhi 0(%r3), 0
224+
; CHECK: br %r14
225+
%res = call i32 @llvm.s390.tend()
226+
%cmp = icmp eq i32 %res, 2
227+
br i1 %cmp, label %if.then, label %if.end
228+
229+
if.then: ; preds = %entry
230+
store i32 0, i32* %ptr, align 4
231+
br label %if.end
232+
233+
if.end: ; preds = %if.then, %entry
234+
ret i32 %res
235+
}
236+
237+
; TABORT with register only.
238+
define void @test_tabort1(i64 %val) {
239+
; CHECK-LABEL: test_tabort1:
240+
; CHECK: tabort 0(%r2)
241+
; CHECK: br %r14
242+
call void @llvm.s390.tabort(i64 %val)
243+
ret void
244+
}
245+
246+
; TABORT with immediate only.
247+
define void @test_tabort2(i64 %val) {
248+
; CHECK-LABEL: test_tabort2:
249+
; CHECK: tabort 1234
250+
; CHECK: br %r14
251+
call void @llvm.s390.tabort(i64 1234)
252+
ret void
253+
}
254+
255+
; TABORT with register + immediate.
256+
define void @test_tabort3(i64 %val) {
257+
; CHECK-LABEL: test_tabort3:
258+
; CHECK: tabort 1234(%r2)
259+
; CHECK: br %r14
260+
%sum = add i64 %val, 1234
261+
call void @llvm.s390.tabort(i64 %sum)
262+
ret void
263+
}
264+
265+
; TABORT with out-of-range immediate.
266+
define void @test_tabort4(i64 %val) {
267+
; CHECK-LABEL: test_tabort4:
268+
; CHECK: tabort 0({{%r[1-5]}})
269+
; CHECK: br %r14
270+
call void @llvm.s390.tabort(i64 4096)
271+
ret void
272+
}
273+
274+
; NTSTG with base pointer only.
275+
define void @test_ntstg1(i64 *%ptr, i64 %val) {
276+
; CHECK-LABEL: test_ntstg1:
277+
; CHECK: ntstg %r3, 0(%r2)
278+
; CHECK: br %r14
279+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
280+
ret void
281+
}
282+
283+
; NTSTG with base and index.
284+
; Check that VSTL doesn't allow an index.
285+
define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
286+
; CHECK-LABEL: test_ntstg2:
287+
; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
288+
; CHECK: ntstg %r4, 0([[REG]],%r2)
289+
; CHECK: br %r14
290+
%ptr = getelementptr i64, i64 *%base, i64 %index
291+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
292+
ret void
293+
}
294+
295+
; NTSTG with the highest in-range displacement.
296+
define void @test_ntstg3(i64 *%base, i64 %val) {
297+
; CHECK-LABEL: test_ntstg3:
298+
; CHECK: ntstg %r3, 524280(%r2)
299+
; CHECK: br %r14
300+
%ptr = getelementptr i64, i64 *%base, i64 65535
301+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
302+
ret void
303+
}
304+
305+
; NTSTG with an out-of-range positive displacement.
306+
define void @test_ntstg4(i64 *%base, i64 %val) {
307+
; CHECK-LABEL: test_ntstg4:
308+
; CHECK: ntstg %r3, 0({{%r[1-5]}})
309+
; CHECK: br %r14
310+
%ptr = getelementptr i64, i64 *%base, i64 65536
311+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
312+
ret void
313+
}
314+
315+
; NTSTG with the lowest in-range displacement.
316+
define void @test_ntstg5(i64 *%base, i64 %val) {
317+
; CHECK-LABEL: test_ntstg5:
318+
; CHECK: ntstg %r3, -524288(%r2)
319+
; CHECK: br %r14
320+
%ptr = getelementptr i64, i64 *%base, i64 -65536
321+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
322+
ret void
323+
}
324+
325+
; NTSTG with an out-of-range negative displacement.
326+
define void @test_ntstg6(i64 *%base, i64 %val) {
327+
; CHECK-LABEL: test_ntstg6:
328+
; CHECK: ntstg %r3, 0({{%r[1-5]}})
329+
; CHECK: br %r14
330+
%ptr = getelementptr i64, i64 *%base, i64 -65537
331+
call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
332+
ret void
333+
}
334+
335+
; ETND.
336+
define i32 @test_etnd() {
337+
; CHECK-LABEL: test_etnd:
338+
; CHECK: etnd %r2
339+
; CHECK: br %r14
340+
%res = call i32 @llvm.s390.etnd()
341+
ret i32 %res
342+
}
343+
344+
; PPA (Transaction-Abort Assist)
345+
define void @test_ppa_txassist(i32 %val) {
346+
; CHECK-LABEL: test_ppa_txassist:
347+
; CHECK: ppa %r2, 0, 1
348+
; CHECK: br %r14
349+
call void @llvm.s390.ppa.txassist(i32 %val)
350+
ret void
351+
}
352+

‎llvm/test/MC/Disassembler/SystemZ/insns.txt

+141
Original file line numberDiff line numberDiff line change
@@ -2503,6 +2503,15 @@
25032503
# CHECK: ear %r15, %a15
25042504
0xb2 0x4f 0x00 0xff
25052505

2506+
# CHECK: etnd %r0
2507+
0xb2 0xec 0x00 0x00
2508+
2509+
# CHECK: etnd %r15
2510+
0xb2 0xec 0x00 0xf0
2511+
2512+
# CHECK: etnd %r7
2513+
0xb2 0xec 0x00 0x70
2514+
25062515
# CHECK: fidbr %f0, 0, %f0
25072516
0xb3 0x5f 0x00 0x00
25082517

@@ -6034,6 +6043,36 @@
60346043
# CHECK: ny %r15, 0
60356044
0xe3 0xf0 0x00 0x00 0x00 0x54
60366045

6046+
# CHECK: ntstg %r0, -524288
6047+
0xe3 0x00 0x00 0x00 0x80 0x25
6048+
6049+
# CHECK: ntstg %r0, -1
6050+
0xe3 0x00 0x0f 0xff 0xff 0x25
6051+
6052+
# CHECK: ntstg %r0, 0
6053+
0xe3 0x00 0x00 0x00 0x00 0x25
6054+
6055+
# CHECK: ntstg %r0, 1
6056+
0xe3 0x00 0x00 0x01 0x00 0x25
6057+
6058+
# CHECK: ntstg %r0, 524287
6059+
0xe3 0x00 0x0f 0xff 0x7f 0x25
6060+
6061+
# CHECK: ntstg %r0, 0(%r1)
6062+
0xe3 0x00 0x10 0x00 0x00 0x25
6063+
6064+
# CHECK: ntstg %r0, 0(%r15)
6065+
0xe3 0x00 0xf0 0x00 0x00 0x25
6066+
6067+
# CHECK: ntstg %r0, 524287(%r1,%r15)
6068+
0xe3 0x01 0xff 0xff 0x7f 0x25
6069+
6070+
# CHECK: ntstg %r0, 524287(%r15,%r1)
6071+
0xe3 0x0f 0x1f 0xff 0x7f 0x25
6072+
6073+
# CHECK: ntstg %r15, 0
6074+
0xe3 0xf0 0x00 0x00 0x00 0x25
6075+
60376076
# CHECK: oc 0(1), 0
60386077
0xd6 0x00 0x00 0x00 0x00 0x00
60396078

@@ -6346,6 +6385,21 @@
63466385
# CHECK: popcnt %r7, %r8
63476386
0xb9 0xe1 0x00 0x78
63486387

6388+
# CHECK: ppa %r0, %r0, 0
6389+
0xb2 0xe8 0x00 0x00
6390+
6391+
# CHECK: ppa %r0, %r0, 15
6392+
0xb2 0xe8 0xf0 0x00
6393+
6394+
# CHECK: ppa %r0, %r15, 0
6395+
0xb2 0xe8 0x00 0x0f
6396+
6397+
# CHECK: ppa %r4, %r6, 7
6398+
0xb2 0xe8 0x70 0x46
6399+
6400+
# CHECK: ppa %r15, %r0, 0
6401+
0xb2 0xe8 0x00 0xf0
6402+
63496403
# CHECK: risbg %r0, %r0, 0, 0, 0
63506404
0xec 0x00 0x00 0x00 0x00 0x55
63516405

@@ -8062,6 +8116,93 @@
80628116
# CHECK: sy %r15, 0
80638117
0xe3 0xf0 0x00 0x00 0x00 0x5b
80648118

8119+
# CHECK: tabort 0
8120+
0xb2 0xfc 0x00 0x00
8121+
8122+
# CHECK: tabort 0(%r1)
8123+
0xb2 0xfc 0x10 0x00
8124+
8125+
# CHECK: tabort 0(%r15)
8126+
0xb2 0xfc 0xf0 0x00
8127+
8128+
# CHECK: tabort 4095
8129+
0xb2 0xfc 0x0f 0xff
8130+
8131+
# CHECK: tabort 4095(%r1)
8132+
0xb2 0xfc 0x1f 0xff
8133+
8134+
# CHECK: tabort 4095(%r15)
8135+
0xb2 0xfc 0xff 0xff
8136+
8137+
# CHECK: tbegin 0, 0
8138+
0xe5 0x60 0x00 0x00 0x00 0x00
8139+
8140+
# CHECK: tbegin 4095, 0
8141+
0xe5 0x60 0x0f 0xff 0x00 0x00
8142+
8143+
# CHECK: tbegin 0, 0
8144+
0xe5 0x60 0x00 0x00 0x00 0x00
8145+
8146+
# CHECK: tbegin 0, 1
8147+
0xe5 0x60 0x00 0x00 0x00 0x01
8148+
8149+
# CHECK: tbegin 0, 32767
8150+
0xe5 0x60 0x00 0x00 0x7f 0xff
8151+
8152+
# CHECK: tbegin 0, 32768
8153+
0xe5 0x60 0x00 0x00 0x80 0x00
8154+
8155+
# CHECK: tbegin 0, 65535
8156+
0xe5 0x60 0x00 0x00 0xff 0xff
8157+
8158+
# CHECK: tbegin 0(%r1), 42
8159+
0xe5 0x60 0x10 0x00 0x00 0x2a
8160+
8161+
# CHECK: tbegin 0(%r15), 42
8162+
0xe5 0x60 0xf0 0x00 0x00 0x2a
8163+
8164+
# CHECK: tbegin 4095(%r1), 42
8165+
0xe5 0x60 0x1f 0xff 0x00 0x2a
8166+
8167+
# CHECK: tbegin 4095(%r15), 42
8168+
0xe5 0x60 0xff 0xff 0x00 0x2a
8169+
8170+
# CHECK: tbeginc 0, 0
8171+
0xe5 0x61 0x00 0x00 0x00 0x00
8172+
8173+
# CHECK: tbeginc 4095, 0
8174+
0xe5 0x61 0x0f 0xff 0x00 0x00
8175+
8176+
# CHECK: tbeginc 0, 0
8177+
0xe5 0x61 0x00 0x00 0x00 0x00
8178+
8179+
# CHECK: tbeginc 0, 1
8180+
0xe5 0x61 0x00 0x00 0x00 0x01
8181+
8182+
# CHECK: tbeginc 0, 32767
8183+
0xe5 0x61 0x00 0x00 0x7f 0xff
8184+
8185+
# CHECK: tbeginc 0, 32768
8186+
0xe5 0x61 0x00 0x00 0x80 0x00
8187+
8188+
# CHECK: tbeginc 0, 65535
8189+
0xe5 0x61 0x00 0x00 0xff 0xff
8190+
8191+
# CHECK: tbeginc 0(%r1), 42
8192+
0xe5 0x61 0x10 0x00 0x00 0x2a
8193+
8194+
# CHECK: tbeginc 0(%r15), 42
8195+
0xe5 0x61 0xf0 0x00 0x00 0x2a
8196+
8197+
# CHECK: tbeginc 4095(%r1), 42
8198+
0xe5 0x61 0x1f 0xff 0x00 0x2a
8199+
8200+
# CHECK: tbeginc 4095(%r15), 42
8201+
0xe5 0x61 0xff 0xff 0x00 0x2a
8202+
8203+
# CHECK: tend
8204+
0xb2 0xf8 0x00 0x00
8205+
80658206
# CHECK: tm 0, 0
80668207
0x91 0x00 0x00 0x00
80678208

‎llvm/test/MC/SystemZ/insn-bad-z196.s

+36
Original file line numberDiff line numberDiff line change
@@ -244,6 +244,11 @@
244244
cxlgbr %f0, 16, %r0, 0
245245
cxlgbr %f2, 0, %r0, 0
246246

247+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
248+
#CHECK: etnd %r7
249+
250+
etnd %r7
251+
247252
#CHECK: error: invalid operand
248253
#CHECK: fidbra %f0, 0, %f0, -1
249254
#CHECK: error: invalid operand
@@ -546,6 +551,16 @@
546551
locr %r0,%r0,-1
547552
locr %r0,%r0,16
548553

554+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
555+
#CHECK: ntstg %r0, 524287(%r1,%r15)
556+
557+
ntstg %r0, 524287(%r1,%r15)
558+
559+
#CHECK: error: {{(instruction requires: processor-assist)?}}
560+
#CHECK: ppa %r4, %r6, 7
561+
562+
ppa %r4, %r6, 7
563+
549564
#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
550565
#CHECK: risbgn %r1, %r2, 0, 0, 0
551566

@@ -690,3 +705,24 @@
690705
stocg %r0,-524289,1
691706
stocg %r0,524288,1
692707
stocg %r0,0(%r1,%r2),1
708+
709+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
710+
#CHECK: tabort 4095(%r1)
711+
712+
tabort 4095(%r1)
713+
714+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
715+
#CHECK: tbegin 4095(%r1), 42
716+
717+
tbegin 4095(%r1), 42
718+
719+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
720+
#CHECK: tbeginc 4095(%r1), 42
721+
722+
tbeginc 4095(%r1), 42
723+
724+
#CHECK: error: {{(instruction requires: transactional-execution)?}}
725+
#CHECK: tend
726+
727+
tend
728+

‎llvm/test/MC/SystemZ/insn-bad-zEC12.s

+60
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,22 @@
22
# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t
33
# RUN: FileCheck < %t %s
44

5+
#CHECK: error: invalid operand
6+
#CHECK: ntstg %r0, -524289
7+
#CHECK: error: invalid operand
8+
#CHECK: ntstg %r0, 524288
9+
10+
ntstg %r0, -524289
11+
ntstg %r0, 524288
12+
13+
#CHECK: error: invalid operand
14+
#CHECK: ppa %r0, %r0, -1
15+
#CHECK: error: invalid operand
16+
#CHECK: ppa %r0, %r0, 16
17+
18+
ppa %r0, %r0, -1
19+
ppa %r0, %r0, 16
20+
521
#CHECK: error: invalid operand
622
#CHECK: risbgn %r0,%r0,0,0,-1
723
#CHECK: error: invalid operand
@@ -22,3 +38,47 @@
2238
risbgn %r0,%r0,-1,0,0
2339
risbgn %r0,%r0,256,0,0
2440

41+
#CHECK: error: invalid operand
42+
#CHECK: tabort -1
43+
#CHECK: error: invalid operand
44+
#CHECK: tabort 4096
45+
#CHECK: error: invalid use of indexed addressing
46+
#CHECK: tabort 0(%r1,%r2)
47+
48+
tabort -1
49+
tabort 4096
50+
tabort 0(%r1,%r2)
51+
52+
#CHECK: error: invalid operand
53+
#CHECK: tbegin -1, 0
54+
#CHECK: error: invalid operand
55+
#CHECK: tbegin 4096, 0
56+
#CHECK: error: invalid use of indexed addressing
57+
#CHECK: tbegin 0(%r1,%r2), 0
58+
#CHECK: error: invalid operand
59+
#CHECK: tbegin 0, -1
60+
#CHECK: error: invalid operand
61+
#CHECK: tbegin 0, 65536
62+
63+
tbegin -1, 0
64+
tbegin 4096, 0
65+
tbegin 0(%r1,%r2), 0
66+
tbegin 0, -1
67+
tbegin 0, 65536
68+
69+
#CHECK: error: invalid operand
70+
#CHECK: tbeginc -1, 0
71+
#CHECK: error: invalid operand
72+
#CHECK: tbeginc 4096, 0
73+
#CHECK: error: invalid use of indexed addressing
74+
#CHECK: tbeginc 0(%r1,%r2), 0
75+
#CHECK: error: invalid operand
76+
#CHECK: tbeginc 0, -1
77+
#CHECK: error: invalid operand
78+
#CHECK: tbeginc 0, 65536
79+
80+
tbeginc -1, 0
81+
tbeginc 4096, 0
82+
tbeginc 0(%r1,%r2), 0
83+
tbeginc 0, -1
84+
tbeginc 0, 65536

‎llvm/test/MC/SystemZ/insn-good-zEC12.s

+107
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,48 @@
11
# For zEC12 and above.
22
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s
33

4+
#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00]
5+
#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0]
6+
#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70]
7+
8+
etnd %r0
9+
etnd %r15
10+
etnd %r7
11+
12+
#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
13+
#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
14+
#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
15+
#CHECK: ntstg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
16+
#CHECK: ntstg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
17+
#CHECK: ntstg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
18+
#CHECK: ntstg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
19+
#CHECK: ntstg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
20+
#CHECK: ntstg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
21+
#CHECK: ntstg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
22+
23+
ntstg %r0, -524288
24+
ntstg %r0, -1
25+
ntstg %r0, 0
26+
ntstg %r0, 1
27+
ntstg %r0, 524287
28+
ntstg %r0, 0(%r1)
29+
ntstg %r0, 0(%r15)
30+
ntstg %r0, 524287(%r1,%r15)
31+
ntstg %r0, 524287(%r15,%r1)
32+
ntstg %r15, 0
33+
34+
#CHECK: ppa %r0, %r0, 0 # encoding: [0xb2,0xe8,0x00,0x00]
35+
#CHECK: ppa %r0, %r0, 15 # encoding: [0xb2,0xe8,0xf0,0x00]
36+
#CHECK: ppa %r0, %r15, 0 # encoding: [0xb2,0xe8,0x00,0x0f]
37+
#CHECK: ppa %r4, %r6, 7 # encoding: [0xb2,0xe8,0x70,0x46]
38+
#CHECK: ppa %r15, %r0, 0 # encoding: [0xb2,0xe8,0x00,0xf0]
39+
40+
ppa %r0, %r0, 0
41+
ppa %r0, %r0, 15
42+
ppa %r0, %r15, 0
43+
ppa %r4, %r6, 7
44+
ppa %r15, %r0, 0
45+
446
#CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
547
#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
648
#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
@@ -17,3 +59,68 @@
1759
risbgn %r15,%r0,0,0,0
1860
risbgn %r4,%r5,6,7,8
1961

62+
#CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00]
63+
#CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00]
64+
#CHECK: tabort 0(%r15) # encoding: [0xb2,0xfc,0xf0,0x00]
65+
#CHECK: tabort 4095 # encoding: [0xb2,0xfc,0x0f,0xff]
66+
#CHECK: tabort 4095(%r1) # encoding: [0xb2,0xfc,0x1f,0xff]
67+
#CHECK: tabort 4095(%r15) # encoding: [0xb2,0xfc,0xff,0xff]
68+
69+
tabort 0
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tabort 0(%r1)
71+
tabort 0(%r15)
72+
tabort 4095
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tabort 4095(%r1)
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tabort 4095(%r15)
75+
76+
#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
77+
#CHECK: tbegin 4095, 0 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
78+
#CHECK: tbegin 0, 0 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
79+
#CHECK: tbegin 0, 1 # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
80+
#CHECK: tbegin 0, 32767 # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
81+
#CHECK: tbegin 0, 32768 # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
82+
#CHECK: tbegin 0, 65535 # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
83+
#CHECK: tbegin 0(%r1), 42 # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
84+
#CHECK: tbegin 0(%r15), 42 # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
85+
#CHECK: tbegin 4095(%r1), 42 # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
86+
#CHECK: tbegin 4095(%r15), 42 # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
87+
88+
tbegin 0, 0
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tbegin 4095, 0
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tbegin 0, 0
91+
tbegin 0, 1
92+
tbegin 0, 32767
93+
tbegin 0, 32768
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tbegin 0, 65535
95+
tbegin 0(%r1), 42
96+
tbegin 0(%r15), 42
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tbegin 4095(%r1), 42
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tbegin 4095(%r15), 42
99+
100+
#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
101+
#CHECK: tbeginc 4095, 0 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
102+
#CHECK: tbeginc 0, 0 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
103+
#CHECK: tbeginc 0, 1 # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
104+
#CHECK: tbeginc 0, 32767 # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
105+
#CHECK: tbeginc 0, 32768 # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
106+
#CHECK: tbeginc 0, 65535 # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
107+
#CHECK: tbeginc 0(%r1), 42 # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
108+
#CHECK: tbeginc 0(%r15), 42 # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
109+
#CHECK: tbeginc 4095(%r1), 42 # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
110+
#CHECK: tbeginc 4095(%r15), 42 # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
111+
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tbeginc 0, 0
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tbeginc 4095, 0
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tbeginc 0, 0
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tbeginc 0, 1
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tbeginc 0, 32767
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tbeginc 0, 32768
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tbeginc 0, 65535
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tbeginc 0(%r1), 42
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tbeginc 0(%r15), 42
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tbeginc 4095(%r1), 42
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tbeginc 4095(%r15), 42
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#CHECK: tend # encoding: [0xb2,0xf8,0x00,0x00]
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tend

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