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gariousgarious
committedJan 19, 2015
[AArch64] Implement GHC calling convention
Original patch by Luke Iannini. Minor improvements and test added by Erik de Castro Lopo. Differential Revision: http://reviews.llvm.org/D6877 From: Erik de Castro Lopo <erikd@mega-nerd.com> llvm-svn: 226473
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‎llvm/lib/Target/AArch64/AArch64CallingConvention.td

+39
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,44 @@ def RetCC_AArch64_WebKit_JS : CallingConv<[
204204
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
205205
]>;
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//===----------------------------------------------------------------------===//
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// ARM64 Calling Convention for GHC
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//===----------------------------------------------------------------------===//
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// This calling convention is specific to the Glasgow Haskell Compiler.
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// The only documentation is the GHC source code, specifically the C header
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// file:
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//
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// https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h
216+
//
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// which defines the registers for the Spineless Tagless G-Machine (STG) that
218+
// GHC uses to implement lazy evaluation. The generic STG machine has a set of
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// registers which are mapped to appropriate set of architecture specific
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// registers for each CPU architecture.
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//
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// The STG Machine is documented here:
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//
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// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode
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//
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// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI
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// register mapping".
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def CC_AArch64_GHC : CallingConv<[
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// Handle all vector types as either f64 or v2f64.
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
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CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>,
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CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>,
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// Promote i8/i16/i32 arguments to i64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
242+
CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>>
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]>;
244+
207245
// FIXME: LR is only callee-saved in the sense that *we* preserve it and are
208246
// presumably a callee to someone. External functions may not do so, but this
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// is currently safe since BL has LR as an implicit-def and what happens after a
@@ -249,3 +287,4 @@ def CSR_AArch64_AllRegs
249287
(sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
250288
(sequence "Q%u", 0, 31))>;
251289

290+
def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;

‎llvm/lib/Target/AArch64/AArch64FastISel.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,8 @@ static unsigned getImplicitScaleFactor(MVT VT) {
302302
CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
303303
if (CC == CallingConv::WebKit_JS)
304304
return CC_AArch64_WebKit_JS;
305+
if (CC == CallingConv::GHC)
306+
return CC_AArch64_GHC;
305307
return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
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}
307309

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

+10
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,11 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
215215
bool HasFP = hasFP(MF);
216216
DebugLoc DL = MBB.findDebugLoc(MBBI);
217217

218+
// All calls are tail calls in GHC calling conv, and functions have no
219+
// prologue/epilogue.
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if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
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return;
222+
218223
int NumBytes = (int)MFI->getStackSize();
219224
if (!AFI->hasStackFrame()) {
220225
assert(!HasFP && "unexpected function without stack frame but with FP");
@@ -451,6 +456,11 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
451456
int NumBytes = MFI->getStackSize();
452457
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
453458

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// All calls are tail calls in GHC calling conv, and functions have no
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// prologue/epilogue.
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if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
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return;
463+
454464
// Initial and residual are named for consitency with the prologue. Note that
455465
// in the epilogue, the residual adjustment is executed first.
456466
uint64_t ArgumentPopSize = 0;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+2
Original file line numberDiff line numberDiff line change
@@ -1990,6 +1990,8 @@ CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
19901990
llvm_unreachable("Unsupported calling convention.");
19911991
case CallingConv::WebKit_JS:
19921992
return CC_AArch64_WebKit_JS;
1993+
case CallingConv::GHC:
1994+
return CC_AArch64_GHC;
19931995
case CallingConv::C:
19941996
case CallingConv::Fast:
19951997
if (!Subtarget->isTargetDarwin())

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

+9-1
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@ AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo *tii,
4040
const MCPhysReg *
4141
AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4242
assert(MF && "Invalid MachineFunction pointer.");
43+
if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
44+
// GHC set of callee saved regs is empty as all those regs are
45+
// used for passing STG regs around
46+
return CSR_AArch64_NoRegs_SaveList;
4347
if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
4448
return CSR_AArch64_AllRegs_SaveList;
4549
else
@@ -48,6 +52,9 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4852

4953
const uint32_t *
5054
AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
55+
if (CC == CallingConv::GHC)
56+
// This is academic becase all GHC calls are (supposed to be) tail calls
57+
return CSR_AArch64_NoRegs_RegMask;
5158
if (CC == CallingConv::AnyReg)
5259
return CSR_AArch64_AllRegs_RegMask;
5360
else
@@ -63,14 +70,15 @@ const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
6370
}
6471

6572
const uint32_t *
66-
AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const {
73+
AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const {
6774
// This should return a register mask that is the same as that returned by
6875
// getCallPreservedMask but that additionally preserves the register used for
6976
// the first i64 argument (which must also be the register used to return a
7077
// single i64 return value)
7178
//
7279
// In case that the calling convention does not use the same register for
7380
// both, the function should return NULL (does not currently apply)
81+
assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
7482
return CSR_AArch64_AAPCS_ThisReturn_RegMask;
7583
}
7684

‎llvm/test/CodeGen/AArch64/ghc-cc.ll

+89
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
2+
3+
; Check the GHC call convention works (aarch64)
4+
5+
@base = external global i64 ; assigned to register: r19
6+
@sp = external global i64 ; assigned to register: r20
7+
@hp = external global i64 ; assigned to register: r21
8+
@r1 = external global i64 ; assigned to register: r22
9+
@r2 = external global i64 ; assigned to register: r23
10+
@r3 = external global i64 ; assigned to register: r24
11+
@r4 = external global i64 ; assigned to register: r25
12+
@r5 = external global i64 ; assigned to register: r26
13+
@r6 = external global i64 ; assigned to register: r27
14+
@splim = external global i64 ; assigned to register: r28
15+
16+
@f1 = external global float ; assigned to register: s8
17+
@f2 = external global float ; assigned to register: s9
18+
@f3 = external global float ; assigned to register: s10
19+
@f4 = external global float ; assigned to register: s11
20+
21+
@d1 = external global double ; assigned to register: d12
22+
@d2 = external global double ; assigned to register: d13
23+
@d3 = external global double ; assigned to register: d14
24+
@d4 = external global double ; assigned to register: d15
25+
26+
define ghccc i64 @addtwo(i64 %x, i64 %y) nounwind {
27+
entry:
28+
; CHECK-LABEL: addtwo
29+
; CHECK: add x0, x19, x20
30+
; CHECK-NEXT: ret
31+
%0 = add i64 %x, %y
32+
ret i64 %0
33+
}
34+
35+
define void @zap(i64 %a, i64 %b) nounwind {
36+
entry:
37+
; CHECK-LABEL: zap
38+
; CHECK-NOT: mov {{x[0-9]+}}, sp
39+
; CHECK: bl addtwo
40+
; CHECK-NEXT: bl foo
41+
%0 = call ghccc i64 @addtwo(i64 %a, i64 %b)
42+
call void @foo() nounwind
43+
ret void
44+
}
45+
46+
define ghccc void @foo_i64 () nounwind {
47+
entry:
48+
; CHECK-LABEL: foo_i64
49+
; CHECK: adrp {{x[0-9]+}}, base
50+
; CHECK-NEXT: ldr x19, [{{x[0-9]+}}, :lo12:base]
51+
; CHECK-NEXT: bl bar_i64
52+
; CHECK-NEXT: ret
53+
54+
%0 = load i64* @base
55+
tail call ghccc void @bar_i64( i64 %0 ) nounwind
56+
ret void
57+
}
58+
59+
define ghccc void @foo_float () nounwind {
60+
entry:
61+
; CHECK-LABEL: foo_float
62+
; CHECK: adrp {{x[0-9]+}}, f1
63+
; CHECK-NEXT: ldr s8, [{{x[0-9]+}}, :lo12:f1]
64+
; CHECK-NEXT: bl bar_float
65+
; CHECK-NEXT: ret
66+
67+
%0 = load float* @f1
68+
tail call ghccc void @bar_float( float %0 ) nounwind
69+
ret void
70+
}
71+
72+
define ghccc void @foo_double () nounwind {
73+
entry:
74+
; CHECK-LABEL: foo_double
75+
; CHECK: adrp {{x[0-9]+}}, d1
76+
; CHECK-NEXT: ldr d12, [{{x[0-9]+}}, :lo12:d1]
77+
; CHECK-NEXT: bl bar_double
78+
; CHECK-NEXT: ret
79+
80+
%0 = load double* @d1
81+
tail call ghccc void @bar_double( double %0 ) nounwind
82+
ret void
83+
}
84+
85+
declare ghccc void @foo ()
86+
87+
declare ghccc void @bar_i64 (i64)
88+
declare ghccc void @bar_float (float)
89+
declare ghccc void @bar_double (double)

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