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Hao LiuHao Liu
Hao Liu
authored and
Hao Liu
committedNov 19, 2014
[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.
SeparateConstOffsetFromGEP can gives more optimizaiton opportunities related to GEPs, which benefits EarlyCSE and LICM. By enabling these passes we can have better address calculations and generate a better addressing mode. Some SPEC 2006 benchmarks (astar, gobmk, namd) have obvious improvements on Cortex-A57. Reviewed in http://reviews.llvm.org/D5864. llvm-svn: 222331
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llvmorg-21-initllvmorg-3.5.2-rc1
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‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

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Original file line numberDiff line numberDiff line change
@@ -81,6 +81,11 @@ EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
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cl::desc("Work around Cortex-A53 erratum 835769"),
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cl::init(false));
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static cl::opt<bool>
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EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(true));
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extern "C" void LLVMInitializeAArch64Target() {
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// Register the target.
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RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
@@ -205,6 +210,19 @@ void AArch64PassConfig::addIRPasses() {
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addPass(createCFGSimplificationPass());
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TargetPassConfig::addIRPasses();
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if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
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// Call SeparateConstOffsetFromGEP pass to extract constants within indices
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// and lower a GEP with multiple indices to either arithmetic operations or
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// multiple GEPs with single index.
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addPass(createSeparateConstOffsetFromGEPPass(TM, true));
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// Call EarlyCSE pass to find and remove subexpressions in the lowered
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// result.
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addPass(createEarlyCSEPass());
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// Do loop invariant code motion in case part of the lowered result is
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// invariant.
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addPass(createLICMPass());
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}
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}
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// Pass Pipeline Configuration

‎llvm/test/CodeGen/AArch64/aarch64-gep-opt.ll

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@@ -0,0 +1,163 @@
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; RUN: llc -O3 -verify-machineinstrs %s -o - | FileCheck %s
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; RUN: llc -O3 -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s
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; RUN: llc -O3 -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-linux-gnueabi"
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; Following test cases test enabling SeparateConstOffsetFromGEP pass in AArch64
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; backend. If useAA() returns true, it will lower a GEP with multiple indices
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; into GEPs with a single index, otherwise it will lower it into a
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; "ptrtoint+arithmetics+inttoptr" form.
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%struct = type { i32, i32, i32, i32, [20 x i32] }
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; Check that when two complex GEPs are used in two basic blocks, LLVM can
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; elimilate the common subexpression for the second use.
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define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) {
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%liberties = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3
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%1 = load i32* %liberties, align 4
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%cmp = icmp eq i32 %1, %lib
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%origin = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2
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%2 = load i32* %origin, align 4
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store i32 %2, i32* %adj, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; CHECK-LABEL: test_GEP_CSE:
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; CHECK: madd
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; CHECK: ldr
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; CHECK-NOT: madd
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; CHECK:ldr
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; CHECK-NoAA-LABEL: @test_GEP_CSE(
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; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64
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; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
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; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]]
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; CHECK-NoAA: add i64 [[PTR2]], 23052
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; CHECK-NoAA: inttoptr
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; CHECK-NoAA: if.then:
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; CHECK-NoAA-NOT: ptrtoint
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; CHECK-NoAA-NOT: mul
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; CHECK-NoAA: add i64 [[PTR2]], 23048
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; CHECK-NoAA: inttoptr
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; CHECK-UseAA-LABEL: @test_GEP_CSE(
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; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8*
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; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96
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; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8* [[PTR0]], i64 [[IDX]]
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; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23052
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; CHECK-UseAA: bitcast
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; CHECK-UseAA: if.then:
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; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23048
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; CHECK-UseAA: bitcast
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%class.my = type { i32, [128 x i32], i32, [256 x %struct.pt]}
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%struct.pt = type { %struct.point*, i32, i32 }
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%struct.point = type { i32, i32 }
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; Check when a GEP is used across two basic block, LLVM can sink the address
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; calculation and code gen can generate a better addressing mode for the second
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; use.
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define void @test_GEP_across_BB(%class.my* %this, i64 %idx) {
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%1 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 1
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%2 = load i32* %1, align 4
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%3 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 2
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%4 = load i32* %3, align 4
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%5 = icmp eq i32 %2, %4
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br i1 %5, label %if.true, label %exit
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if.true:
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%6 = shl i32 %4, 1
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store i32 %6, i32* %3, align 4
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br label %exit
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exit:
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%7 = add nsw i32 %4, 1
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store i32 %7, i32* %1, align 4
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ret void
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}
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; CHECK-LABEL: test_GEP_across_BB:
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #528]
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #532]
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; CHECK-NOT: add
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; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #532]
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; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #528]
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; CHECK-NoAA-LABEL: test_GEP_across_BB(
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; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528
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; CHECK-NoAA: add i64 [[TMP]], 532
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; CHECK-NoAA: if.true:
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; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532
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; CHECK-NoAA: exit:
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; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528
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; CHECK-UseAA-LABEL: test_GEP_across_BB(
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; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr
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; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 528
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; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 532
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; CHECK-UseAA: if.true:
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; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 532
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; CHECK-UseAA: exit:
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; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 528
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%struct.S = type { float, double }
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@struct_array = global [1024 x %struct.S] zeroinitializer, align 16
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; The following two test cases check we can extract constant from indices of
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; struct type.
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; The constant offsets are from indices "i64 %idxprom" and "i32 1". As the
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; alloca size of %struct.S is 16, and "i32 1" is the 2rd element whose field
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; offset is 8, the total constant offset is (5 * 16 + 8) = 88.
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define double* @test-struct_1(i32 %i) {
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entry:
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%add = add nsw i32 %i, 5
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%idxprom = sext i32 %add to i64
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%p = getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1
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ret double* %p
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}
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; CHECK-NoAA-LABEL: @test-struct_1(
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; CHECK-NoAA-NOT: getelementptr
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; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88
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; CHECK-UseAA-LABEL: @test-struct_1(
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; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 88
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%struct3 = type { i64, i32 }
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%struct2 = type { %struct3, i32 }
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%struct1 = type { i64, %struct2 }
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%struct0 = type { i32, i32, i64*, [100 x %struct1] }
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; The constant offsets are from indices "i32 3", "i64 %arrayidx" and "i32 1".
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; "i32 3" is the 4th element whose field offset is 16. The alloca size of
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; %struct1 is 32. "i32 1" is the 2rd element whose field offset is 8. So the
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; total constant offset is 16 + (-2 * 32) + 8 = -40
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define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) {
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entry:
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%arrayidx = add nsw i64 %idx, -2
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%ptr2 = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1
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ret %struct2* %ptr2
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}
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; CHECK-NoAA-LABEL: @test-struct_2(
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; CHECK-NoAA-NOT: = getelementptr
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; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40
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; CHECK-UseAA-LABEL: @test-struct_2(
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; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 -40
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; Test that when a index is added from two constant, SeparateConstOffsetFromGEP
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; pass does not generate incorrect result.
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define void @test_const_add([3 x i32]* %in) {
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%inc = add nsw i32 2, 1
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%idxprom = sext i32 %inc to i64
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%arrayidx = getelementptr [3 x i32]* %in, i64 %idxprom, i64 2
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store i32 0, i32* %arrayidx, align 4
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ret void
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}
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; CHECK-LABEL: test_const_add:
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; CHECK: str wzr, [x0, #44]

‎llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll

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@@ -1,4 +1,4 @@
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; RUN: llc -O3 -mtriple arm64-apple-ios3 %s -o - | FileCheck %s
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; RUN: llc -O3 -mtriple arm64-apple-ios3 -aarch64-gep-opt=false %s -o - | FileCheck %s
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; <rdar://problem/13621857>
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@block = common global i8* null, align 8

‎llvm/test/CodeGen/AArch64/arm64-cse.ll

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@@ -1,4 +1,4 @@
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; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 | FileCheck %s
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; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false | FileCheck %s
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target triple = "arm64-apple-ios"
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; rdar://12462006

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