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jholewinski-nvjholewinski-nv
committedJun 27, 2014
[NVPTX] Add support for envreg reads
llvm-svn: 211930
1 parent 602fa5b commit 124fc19

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‎llvm/include/llvm/IR/IntrinsicsNVVM.td

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -889,6 +889,136 @@ def int_nvvm_compiler_error :
889889
def int_nvvm_compiler_warn :
890890
Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.warn">;
891891

892+
// Environment register read
893+
def int_nvvm_read_ptx_sreg_envreg0
894+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
895+
"llvm.nvvm.read.ptx.sreg.envreg0">,
896+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg0">;
897+
def int_nvvm_read_ptx_sreg_envreg1
898+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
899+
"llvm.nvvm.read.ptx.sreg.envreg1">,
900+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg1">;
901+
def int_nvvm_read_ptx_sreg_envreg2
902+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
903+
"llvm.nvvm.read.ptx.sreg.envreg2">,
904+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg2">;
905+
def int_nvvm_read_ptx_sreg_envreg3
906+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
907+
"llvm.nvvm.read.ptx.sreg.envreg3">,
908+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg3">;
909+
def int_nvvm_read_ptx_sreg_envreg4
910+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
911+
"llvm.nvvm.read.ptx.sreg.envreg4">,
912+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg4">;
913+
def int_nvvm_read_ptx_sreg_envreg5
914+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
915+
"llvm.nvvm.read.ptx.sreg.envreg5">,
916+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg5">;
917+
def int_nvvm_read_ptx_sreg_envreg6
918+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
919+
"llvm.nvvm.read.ptx.sreg.envreg6">,
920+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg6">;
921+
def int_nvvm_read_ptx_sreg_envreg7
922+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
923+
"llvm.nvvm.read.ptx.sreg.envreg7">,
924+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg7">;
925+
def int_nvvm_read_ptx_sreg_envreg8
926+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
927+
"llvm.nvvm.read.ptx.sreg.envreg8">,
928+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg8">;
929+
def int_nvvm_read_ptx_sreg_envreg9
930+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
931+
"llvm.nvvm.read.ptx.sreg.envreg9">,
932+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg9">;
933+
def int_nvvm_read_ptx_sreg_envreg10
934+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
935+
"llvm.nvvm.read.ptx.sreg.envreg10">,
936+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg10">;
937+
def int_nvvm_read_ptx_sreg_envreg11
938+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
939+
"llvm.nvvm.read.ptx.sreg.envreg11">,
940+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg11">;
941+
def int_nvvm_read_ptx_sreg_envreg12
942+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
943+
"llvm.nvvm.read.ptx.sreg.envreg12">,
944+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg12">;
945+
def int_nvvm_read_ptx_sreg_envreg13
946+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
947+
"llvm.nvvm.read.ptx.sreg.envreg13">,
948+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg13">;
949+
def int_nvvm_read_ptx_sreg_envreg14
950+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
951+
"llvm.nvvm.read.ptx.sreg.envreg14">,
952+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg14">;
953+
def int_nvvm_read_ptx_sreg_envreg15
954+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
955+
"llvm.nvvm.read.ptx.sreg.envreg15">,
956+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg15">;
957+
def int_nvvm_read_ptx_sreg_envreg16
958+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
959+
"llvm.nvvm.read.ptx.sreg.envreg16">,
960+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg16">;
961+
def int_nvvm_read_ptx_sreg_envreg17
962+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
963+
"llvm.nvvm.read.ptx.sreg.envreg17">,
964+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg17">;
965+
def int_nvvm_read_ptx_sreg_envreg18
966+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
967+
"llvm.nvvm.read.ptx.sreg.envreg18">,
968+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg18">;
969+
def int_nvvm_read_ptx_sreg_envreg19
970+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
971+
"llvm.nvvm.read.ptx.sreg.envreg19">,
972+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg19">;
973+
def int_nvvm_read_ptx_sreg_envreg20
974+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
975+
"llvm.nvvm.read.ptx.sreg.envreg20">,
976+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg20">;
977+
def int_nvvm_read_ptx_sreg_envreg21
978+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
979+
"llvm.nvvm.read.ptx.sreg.envreg21">,
980+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg21">;
981+
def int_nvvm_read_ptx_sreg_envreg22
982+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
983+
"llvm.nvvm.read.ptx.sreg.envreg22">,
984+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg22">;
985+
def int_nvvm_read_ptx_sreg_envreg23
986+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
987+
"llvm.nvvm.read.ptx.sreg.envreg23">,
988+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg23">;
989+
def int_nvvm_read_ptx_sreg_envreg24
990+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
991+
"llvm.nvvm.read.ptx.sreg.envreg24">,
992+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg24">;
993+
def int_nvvm_read_ptx_sreg_envreg25
994+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
995+
"llvm.nvvm.read.ptx.sreg.envreg25">,
996+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg25">;
997+
def int_nvvm_read_ptx_sreg_envreg26
998+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
999+
"llvm.nvvm.read.ptx.sreg.envreg26">,
1000+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg26">;
1001+
def int_nvvm_read_ptx_sreg_envreg27
1002+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
1003+
"llvm.nvvm.read.ptx.sreg.envreg27">,
1004+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg27">;
1005+
def int_nvvm_read_ptx_sreg_envreg28
1006+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
1007+
"llvm.nvvm.read.ptx.sreg.envreg28">,
1008+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg28">;
1009+
def int_nvvm_read_ptx_sreg_envreg29
1010+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
1011+
"llvm.nvvm.read.ptx.sreg.envreg29">,
1012+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg29">;
1013+
def int_nvvm_read_ptx_sreg_envreg30
1014+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
1015+
"llvm.nvvm.read.ptx.sreg.envreg30">,
1016+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg30">;
1017+
def int_nvvm_read_ptx_sreg_envreg31
1018+
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
1019+
"llvm.nvvm.read.ptx.sreg.envreg31">,
1020+
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg31">;
1021+
8921022

8931023
// Texture Fetch
8941024
def int_nvvm_tex_1d_v4f32_i32

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1689,6 +1689,45 @@ def INT_NVVM_COMPILER_ERROR_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
16891689
[(int_nvvm_compiler_error Int64Regs:$a)]>;
16901690

16911691

1692+
// Special register reads
1693+
def MOV_SPECIAL : NVPTXInst<(outs Int32Regs:$d),
1694+
(ins SpecialRegs:$r),
1695+
"mov.b32\t$d, $r;", []>;
1696+
1697+
def : Pat<(int_nvvm_read_ptx_sreg_envreg0), (MOV_SPECIAL ENVREG0)>;
1698+
def : Pat<(int_nvvm_read_ptx_sreg_envreg1), (MOV_SPECIAL ENVREG1)>;
1699+
def : Pat<(int_nvvm_read_ptx_sreg_envreg2), (MOV_SPECIAL ENVREG2)>;
1700+
def : Pat<(int_nvvm_read_ptx_sreg_envreg3), (MOV_SPECIAL ENVREG3)>;
1701+
def : Pat<(int_nvvm_read_ptx_sreg_envreg4), (MOV_SPECIAL ENVREG4)>;
1702+
def : Pat<(int_nvvm_read_ptx_sreg_envreg5), (MOV_SPECIAL ENVREG5)>;
1703+
def : Pat<(int_nvvm_read_ptx_sreg_envreg6), (MOV_SPECIAL ENVREG6)>;
1704+
def : Pat<(int_nvvm_read_ptx_sreg_envreg7), (MOV_SPECIAL ENVREG7)>;
1705+
def : Pat<(int_nvvm_read_ptx_sreg_envreg8), (MOV_SPECIAL ENVREG8)>;
1706+
def : Pat<(int_nvvm_read_ptx_sreg_envreg9), (MOV_SPECIAL ENVREG9)>;
1707+
def : Pat<(int_nvvm_read_ptx_sreg_envreg10), (MOV_SPECIAL ENVREG10)>;
1708+
def : Pat<(int_nvvm_read_ptx_sreg_envreg11), (MOV_SPECIAL ENVREG11)>;
1709+
def : Pat<(int_nvvm_read_ptx_sreg_envreg12), (MOV_SPECIAL ENVREG12)>;
1710+
def : Pat<(int_nvvm_read_ptx_sreg_envreg13), (MOV_SPECIAL ENVREG13)>;
1711+
def : Pat<(int_nvvm_read_ptx_sreg_envreg14), (MOV_SPECIAL ENVREG14)>;
1712+
def : Pat<(int_nvvm_read_ptx_sreg_envreg15), (MOV_SPECIAL ENVREG15)>;
1713+
def : Pat<(int_nvvm_read_ptx_sreg_envreg16), (MOV_SPECIAL ENVREG16)>;
1714+
def : Pat<(int_nvvm_read_ptx_sreg_envreg17), (MOV_SPECIAL ENVREG17)>;
1715+
def : Pat<(int_nvvm_read_ptx_sreg_envreg18), (MOV_SPECIAL ENVREG18)>;
1716+
def : Pat<(int_nvvm_read_ptx_sreg_envreg19), (MOV_SPECIAL ENVREG19)>;
1717+
def : Pat<(int_nvvm_read_ptx_sreg_envreg20), (MOV_SPECIAL ENVREG20)>;
1718+
def : Pat<(int_nvvm_read_ptx_sreg_envreg21), (MOV_SPECIAL ENVREG21)>;
1719+
def : Pat<(int_nvvm_read_ptx_sreg_envreg22), (MOV_SPECIAL ENVREG22)>;
1720+
def : Pat<(int_nvvm_read_ptx_sreg_envreg23), (MOV_SPECIAL ENVREG23)>;
1721+
def : Pat<(int_nvvm_read_ptx_sreg_envreg24), (MOV_SPECIAL ENVREG24)>;
1722+
def : Pat<(int_nvvm_read_ptx_sreg_envreg25), (MOV_SPECIAL ENVREG25)>;
1723+
def : Pat<(int_nvvm_read_ptx_sreg_envreg26), (MOV_SPECIAL ENVREG26)>;
1724+
def : Pat<(int_nvvm_read_ptx_sreg_envreg27), (MOV_SPECIAL ENVREG27)>;
1725+
def : Pat<(int_nvvm_read_ptx_sreg_envreg28), (MOV_SPECIAL ENVREG28)>;
1726+
def : Pat<(int_nvvm_read_ptx_sreg_envreg29), (MOV_SPECIAL ENVREG29)>;
1727+
def : Pat<(int_nvvm_read_ptx_sreg_envreg30), (MOV_SPECIAL ENVREG30)>;
1728+
def : Pat<(int_nvvm_read_ptx_sreg_envreg31), (MOV_SPECIAL ENVREG31)>;
1729+
1730+
16921731
//-----------------------------------
16931732
// Texture Intrinsics
16941733
//-----------------------------------

‎llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,10 @@ foreach i = 0-4 in {
4646
def da#i : NVPTXReg<"%da"#i>;
4747
}
4848

49+
foreach i = 0-31 in {
50+
def ENVREG#i : NVPTXReg<"%envreg"#i>;
51+
}
52+
4953
//===----------------------------------------------------------------------===//
5054
// Register classes
5155
//===----------------------------------------------------------------------===//
@@ -61,4 +65,5 @@ def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
6165
def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;
6266

6367
// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
64-
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
68+
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot,
69+
(sequence "ENVREG%u", 0, 31))>;

‎llvm/test/CodeGen/NVPTX/envreg.ll

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
2+
3+
4+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
14+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg10()
15+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg11()
16+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg12()
17+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg13()
18+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg14()
19+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg15()
20+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg16()
21+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg17()
22+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg18()
23+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg19()
24+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg20()
25+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg21()
26+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg22()
27+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg23()
28+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg24()
29+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg25()
30+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg26()
31+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg27()
32+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg28()
33+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg29()
34+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg30()
35+
declare i32 @llvm.nvvm.read.ptx.sreg.envreg31()
36+
37+
38+
; CHECK: foo
39+
define i32 @foo() {
40+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg0
41+
%val0 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg0()
42+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1
43+
%val1 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg1()
44+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2
45+
%val2 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg2()
46+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg3
47+
%val3 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg3()
48+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg4
49+
%val4 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg4()
50+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg5
51+
%val5 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg5()
52+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg6
53+
%val6 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg6()
54+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg7
55+
%val7 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg7()
56+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg8
57+
%val8 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg8()
58+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg9
59+
%val9 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg9()
60+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg10
61+
%val10 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg10()
62+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg11
63+
%val11 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg11()
64+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg12
65+
%val12 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg12()
66+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg13
67+
%val13 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg13()
68+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg14
69+
%val14 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg14()
70+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg15
71+
%val15 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg15()
72+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg16
73+
%val16 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg16()
74+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg17
75+
%val17 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg17()
76+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg18
77+
%val18 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg18()
78+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg19
79+
%val19 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg19()
80+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg20
81+
%val20 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg20()
82+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg21
83+
%val21 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg21()
84+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg22
85+
%val22 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg22()
86+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg23
87+
%val23 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg23()
88+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg24
89+
%val24 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg24()
90+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg25
91+
%val25 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg25()
92+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg26
93+
%val26 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg26()
94+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg27
95+
%val27 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg27()
96+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg28
97+
%val28 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg28()
98+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg29
99+
%val29 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg29()
100+
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg30
101+
%val30 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg30()
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; CHECK: mov.b32 %r{{[0-9]+}}, %envreg31
103+
%val31 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg31()
104+
105+
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%ret0 = add i32 %val0, %val1
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%ret1 = add i32 %ret0, %val2
108+
%ret2 = add i32 %ret1, %val3
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%ret3 = add i32 %ret2, %val4
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%ret4 = add i32 %ret3, %val5
111+
%ret5 = add i32 %ret4, %val6
112+
%ret6 = add i32 %ret5, %val7
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%ret7 = add i32 %ret6, %val8
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%ret8 = add i32 %ret7, %val9
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%ret9 = add i32 %ret8, %val10
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%ret10 = add i32 %ret9, %val11
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%ret11 = add i32 %ret10, %val12
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%ret12 = add i32 %ret11, %val13
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%ret13 = add i32 %ret12, %val14
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%ret14 = add i32 %ret13, %val15
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%ret15 = add i32 %ret14, %val16
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%ret16 = add i32 %ret15, %val17
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%ret17 = add i32 %ret16, %val18
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%ret18 = add i32 %ret17, %val19
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%ret19 = add i32 %ret18, %val20
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%ret20 = add i32 %ret19, %val21
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%ret21 = add i32 %ret20, %val22
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%ret22 = add i32 %ret21, %val23
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%ret23 = add i32 %ret22, %val24
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%ret24 = add i32 %ret23, %val25
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%ret25 = add i32 %ret24, %val26
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%ret26 = add i32 %ret25, %val27
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%ret27 = add i32 %ret26, %val28
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%ret28 = add i32 %ret27, %val29
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%ret29 = add i32 %ret28, %val30
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%ret30 = add i32 %ret29, %val31
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ret i32 %ret30
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}

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