Skip to content

Commit 940ab93

Browse files
author
Hal Finkel
committedFeb 28, 2014
Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the condition register bits. These bits can be treated on PowerPC as separate registers; individual bit operations (and, or, xor, etc.) are supported. Tracking booleans in CR bits has several advantages: - Reduction in register pressure (because we no longer need GPRs to store boolean values). - Logical operations on booleans can be handled more efficiently; we used to have to move all results from comparisons into GPRs, perform promoted logical operations in GPRs, and then move the result back into condition register bits to be used by conditional branches. This can be very inefficient, because the throughput of these CR <-> GPR moves have high latency and low throughput (especially when other associated instructions are accounted for). - On the POWER7 and similar cores, we can increase total throughput by using the CR bits. CR bit operations have a dedicated functional unit. Most of this is more-or-less mechanical: Adjustments were needed in the calling-convention code, support was added for spilling/restoring individual condition-register bits, and conditional branch instruction definitions taking specific CR bits were added (plus patterns and code for generating bit-level operations). This is enabled by default when running at -O2 and higher. For -O0 and -O1, where the ability to debug is more important, this feature is disabled by default. Individual CR bits do not have assigned DWARF register numbers, and storing values in CR bits makes them invisible to the debugger. It is critical, however, that we don't move i1 values that have been promoted to larger values (such as those passed as function arguments) into bit registers only to quickly turn around and move the values back into GPRs (such as happens when values are returned by functions). A pair of target-specific DAG combines are added to remove the trunc/extends in: trunc(binary-ops(binary-ops(zext(x), zext(y)), ...) and: zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...) In short, we only want to use CR bits where some of the i1 values come from comparisons or are used by conditional branches or selects. To put it another way, if we can do the entire i1 computation in GPRs, then we probably should (on the POWER7, the GPR-operation throughput is higher, and for all cores, the CR <-> GPR moves are expensive). POWER7 test-suite performance results (from 10 runs in each configuration): SingleSource/Benchmarks/Misc/mandel-2: 35% speedup MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown MultiSource/Applications/lemon/lemon: 8% slowdown llvm-svn: 202451
1 parent 2756dc1 commit 940ab93

30 files changed

+2371
-165
lines changed
 

‎llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,9 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
149149
case PPC::PRED_NU:
150150
O << "nu";
151151
return;
152+
case PPC::PRED_BIT_SET:
153+
case PPC::PRED_BIT_UNSET:
154+
llvm_unreachable("Invalid use of bit predicate code");
152155
}
153156
llvm_unreachable("Invalid predicate code");
154157
}
@@ -184,6 +187,9 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
184187
case PPC::PRED_NU_PLUS:
185188
O << "+";
186189
return;
190+
case PPC::PRED_BIT_SET:
191+
case PPC::PRED_BIT_UNSET:
192+
llvm_unreachable("Invalid use of bit predicate code");
187193
}
188194
llvm_unreachable("Invalid predicate code");
189195
}

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
4242
case PPC::PRED_LE_PLUS: return PPC::PRED_GT_MINUS;
4343
case PPC::PRED_NU_PLUS: return PPC::PRED_UN_MINUS;
4444
case PPC::PRED_UN_PLUS: return PPC::PRED_NU_MINUS;
45+
46+
// Simple predicates for single condition-register bits.
47+
case PPC::PRED_BIT_SET: return PPC::PRED_BIT_UNSET;
48+
case PPC::PRED_BIT_UNSET: return PPC::PRED_BIT_SET;
4549
}
4650
llvm_unreachable("Unknown PPC branch opcode!");
4751
}
@@ -72,6 +76,10 @@ PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) {
7276
case PPC::PRED_LE_PLUS: return PPC::PRED_GE_PLUS;
7377
case PPC::PRED_NU_PLUS: return PPC::PRED_NU_PLUS;
7478
case PPC::PRED_UN_PLUS: return PPC::PRED_UN_PLUS;
79+
80+
case PPC::PRED_BIT_SET:
81+
case PPC::PRED_BIT_UNSET:
82+
llvm_unreachable("Invalid use of bit predicate code");
7583
}
7684
llvm_unreachable("Unknown PPC branch opcode!");
7785
}

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,12 @@ namespace PPC {
4848
PRED_GT_PLUS = (1 << 5) | 15,
4949
PRED_NE_PLUS = (2 << 5) | 7,
5050
PRED_UN_PLUS = (3 << 5) | 15,
51-
PRED_NU_PLUS = (3 << 5) | 7
51+
PRED_NU_PLUS = (3 << 5) | 7,
52+
53+
// When dealing with individual condition-register bits, we have simple set
54+
// and unset predicates.
55+
PRED_BIT_SET = -1,
56+
PRED_BIT_UNSET = -2
5257
};
5358

5459
/// Invert the specified predicate. != -> ==, < -> >=.

‎llvm/lib/Target/PowerPC/PPC.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
5151
"Enable 64-bit instructions">;
5252
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
5353
"Enable 64-bit registers usage for ppc32 [beta]">;
54+
def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
55+
"Use condition-register bits individually">;
5456
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
5557
"Enable Altivec instructions">;
5658
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",

‎llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,9 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
115115
MachineBasicBlock *Dest = 0;
116116
if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
117117
Dest = I->getOperand(2).getMBB();
118+
else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
119+
!I->getOperand(1).isImm())
120+
Dest = I->getOperand(1).getMBB();
118121
else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
119122
I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
120123
!I->getOperand(0).isImm())
@@ -166,6 +169,12 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
166169
// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
167170
BuildMI(MBB, I, dl, TII->get(PPC::BCC))
168171
.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
172+
} else if (I->getOpcode() == PPC::BC) {
173+
unsigned CRBit = I->getOperand(0).getReg();
174+
BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
175+
} else if (I->getOpcode() == PPC::BCn) {
176+
unsigned CRBit = I->getOperand(0).getReg();
177+
BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
169178
} else if (I->getOpcode() == PPC::BDNZ) {
170179
BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
171180
} else if (I->getOpcode() == PPC::BDNZ8) {

‎llvm/lib/Target/PowerPC/PPCCallingConv.td

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
/// CCIfSubtarget - Match if the current subtarget has a feature F.
1616
class CCIfSubtarget<string F, CCAction A>
1717
: CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
18+
class CCIfNotSubtarget<string F, CCAction A>
19+
: CCIf<!strconcat("!State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
1820

1921
//===----------------------------------------------------------------------===//
2022
// Return Value Calling Convention
@@ -23,7 +25,8 @@ class CCIfSubtarget<string F, CCAction A>
2325
// Return-value convention for PowerPC
2426
def RetCC_PPC : CallingConv<[
2527
// On PPC64, integer return values are always promoted to i64
26-
CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
28+
CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
29+
CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
2730

2831
CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
2932
CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
@@ -46,6 +49,7 @@ def RetCC_PPC : CallingConv<[
4649
// Only handle ints and floats. All ints are promoted to i64.
4750
// Vector types and quadword ints are not handled.
4851
def CC_PPC64_ELF_FIS : CallingConv<[
52+
CCIfType<[i1], CCPromoteToType<i64>>,
4953
CCIfType<[i8], CCPromoteToType<i64>>,
5054
CCIfType<[i16], CCPromoteToType<i64>>,
5155
CCIfType<[i32], CCPromoteToType<i64>>,
@@ -58,6 +62,7 @@ def CC_PPC64_ELF_FIS : CallingConv<[
5862
// and multiple register returns are "supported" to avoid compile
5963
// errors, but none are handled by the fast selector.
6064
def RetCC_PPC64_ELF_FIS : CallingConv<[
65+
CCIfType<[i1], CCPromoteToType<i64>>,
6166
CCIfType<[i8], CCPromoteToType<i64>>,
6267
CCIfType<[i16], CCPromoteToType<i64>>,
6368
CCIfType<[i32], CCPromoteToType<i64>>,
@@ -73,6 +78,8 @@ def RetCC_PPC64_ELF_FIS : CallingConv<[
7378
//===----------------------------------------------------------------------===//
7479

7580
def CC_PPC32_SVR4_Common : CallingConv<[
81+
CCIfType<[i1], CCPromoteToType<i32>>,
82+
7683
// The ABI requires i64 to be passed in two adjacent registers with the first
7784
// register having an odd register number.
7885
CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,

‎llvm/lib/Target/PowerPC/PPCFastISel.cpp

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -740,6 +740,9 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
740740
return false;
741741
MVT SrcVT = SrcEVT.getSimpleVT();
742742

743+
if (SrcVT == MVT::i1 && PPCSubTarget.useCRBits())
744+
return false;
745+
743746
// See if operand 2 is an immediate encodeable in the compare.
744747
// FIXME: Operands are not in canonical order at -O0, so an immediate
745748
// operand in position 1 is a lost opportunity for now. We are
@@ -1203,7 +1206,7 @@ bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
12031206

12041207
// Skip vector arguments for now, as well as long double and
12051208
// uint128_t, and anything that isn't passed in a register.
1206-
if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 ||
1209+
if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
12071210
!VA.isRegLoc() || VA.needsCustom())
12081211
return false;
12091212

@@ -1995,6 +1998,15 @@ unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
19951998
// Materialize an integer constant into a register, and return
19961999
// the register number (or zero if we failed to handle it).
19972000
unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
2001+
// If we're using CR bit registers for i1 values, handle that as a special
2002+
// case first.
2003+
if (VT == MVT::i1 && PPCSubTarget.useCRBits()) {
2004+
const ConstantInt *CI = cast<ConstantInt>(C);
2005+
unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2006+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2007+
TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2008+
return ImmReg;
2009+
}
19982010

19992011
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
20002012
VT != MVT::i8 && VT != MVT::i1)
@@ -2160,6 +2172,15 @@ unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
21602172
if (Opc != ISD::Constant)
21612173
return 0;
21622174

2175+
// If we're using CR bit registers for i1 values, handle that as a special
2176+
// case first.
2177+
if (VT == MVT::i1 && PPCSubTarget.useCRBits()) {
2178+
unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2179+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2180+
TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2181+
return ImmReg;
2182+
}
2183+
21632184
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
21642185
VT != MVT::i8 && VT != MVT::i1)
21652186
return 0;

0 commit comments

Comments
 (0)
Please sign in to comment.