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vegovinvegovin
committedJan 6, 2014
[Sparc] Add initial implementation of disassembler for sparc
llvm-svn: 198591
1 parent a45a176 commit dfcccc7

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12 files changed

+457
-61
lines changed

12 files changed

+457
-61
lines changed
 

‎llvm/lib/Target/Sparc/CMakeLists.txt

+2
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@@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
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tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
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tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
@@ -32,3 +33,4 @@ add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(InstPrinter)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)

‎llvm/lib/Target/Sparc/Disassembler/CMakeLists.txt

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@@ -0,0 +1,12 @@
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add_llvm_library(LLVMSparcDisassembler
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SparcDisassembler.cpp
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)
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# workaround for hanging compilation on MSVC9 and 10
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if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500
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OR MSVC_VERSION EQUAL 1600 )
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set_property(
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SOURCE SparcDisassembler.cpp
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PROPERTY COMPILE_FLAGS "/Od"
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)
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endif()

‎llvm/lib/Target/Sparc/Disassembler/LLVMBuild.txt

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@@ -0,0 +1,23 @@
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;===- ./lib/Target/Sparc/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[component_0]
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type = Library
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name = SparcDisassembler
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parent = Sparc
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required_libraries = MC Support SparcInfo
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add_to_library_groups = Sparc

‎llvm/lib/Target/Sparc/Disassembler/Makefile

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@@ -0,0 +1,16 @@
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##===- lib/Target/Sparc/Disassembler/Makefile --------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../../..
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LIBRARYNAME = LLVMSparcDisassembler
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# Hack: we need to include 'main' Sparc target directory to grab private headers
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CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
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include $(LEVEL)/Makefile.common

‎llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

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@@ -0,0 +1,228 @@
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//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Sparc Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sparc-disassembler"
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// SparcDisassembler - a disassembler class for Sparc.
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class SparcDisassembler : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
36+
MCDisassembler(STI), RegInfo(Info)
37+
{}
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virtual ~SparcDisassembler() {}
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const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
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/// getInstruction - See MCDisassembler.
43+
virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
45+
const MemoryObject &region,
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uint64_t address,
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raw_ostream &vStream,
48+
raw_ostream &cStream) const;
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private:
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OwningPtr<const MCRegisterInfo> RegInfo;
51+
};
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}
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namespace llvm {
56+
extern Target TheSparcTarget, TheSparcV9Target;
57+
}
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static MCDisassembler *createSparcDisassembler(
60+
const Target &T,
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const MCSubtargetInfo &STI) {
62+
return new SparcDisassembler(STI, T.createMCRegInfo(""));
63+
}
64+
65+
66+
extern "C" void LLVMInitializeSparcDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
69+
createSparcDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
71+
createSparcDisassembler);
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}
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static const unsigned IntRegDecoderTable[] = {
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SP::G0, SP::G1, SP::G2, SP::G3,
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SP::G4, SP::G5, SP::G6, SP::G7,
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SP::O0, SP::O1, SP::O2, SP::O3,
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SP::O4, SP::O5, SP::O6, SP::O7,
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SP::L0, SP::L1, SP::L2, SP::L3,
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SP::L4, SP::L5, SP::L6, SP::L7,
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SP::I0, SP::I1, SP::I2, SP::I3,
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SP::I4, SP::I5, SP::I6, SP::I7 };
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static const unsigned FPRegDecoderTable[] = {
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SP::F0, SP::F1, SP::F2, SP::F3,
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SP::F4, SP::F5, SP::F6, SP::F7,
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SP::F8, SP::F9, SP::F10, SP::F11,
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SP::F12, SP::F13, SP::F14, SP::F15,
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SP::F16, SP::F17, SP::F18, SP::F19,
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SP::F20, SP::F21, SP::F22, SP::F23,
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SP::F24, SP::F25, SP::F26, SP::F27,
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SP::F28, SP::F29, SP::F30, SP::F31 };
95+
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static const unsigned DFPRegDecoderTable[] = {
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SP::D0, SP::D16, SP::D1, SP::D17,
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SP::D2, SP::D18, SP::D3, SP::D19,
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SP::D4, SP::D20, SP::D5, SP::D21,
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SP::D6, SP::D22, SP::D7, SP::D23,
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SP::D8, SP::D24, SP::D9, SP::D25,
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SP::D10, SP::D26, SP::D11, SP::D27,
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SP::D12, SP::D28, SP::D13, SP::D29,
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SP::D14, SP::D30, SP::D15, SP::D31 };
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static const unsigned QFPRegDecoderTable[] = {
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SP::Q0, SP::Q8, -1, -1,
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SP::Q1, SP::Q9, -1, -1,
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SP::Q2, SP::Q10, -1, -1,
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SP::Q3, SP::Q11, -1, -1,
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SP::Q4, SP::Q12, -1, -1,
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SP::Q5, SP::Q13, -1, -1,
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SP::Q6, SP::Q14, -1, -1,
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SP::Q7, SP::Q15, -1, -1 } ;
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
120+
if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
129+
uint64_t Address,
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const void *Decoder) {
131+
if (RegNo > 31)
132+
return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
143+
if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = FPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
149+
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
155+
if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = DFPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
166+
const void *Decoder) {
167+
if (RegNo > 31)
168+
return MCDisassembler::Fail;
169+
170+
unsigned Reg = QFPRegDecoderTable[RegNo];
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if (Reg == (unsigned)-1)
172+
return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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#include "SparcGenDisassemblerTables.inc"
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word.
182+
static DecodeStatus readInstruction32(const MemoryObject &region,
183+
uint64_t address,
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uint64_t &size,
185+
uint32_t &insn) {
186+
uint8_t Bytes[4];
187+
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// We want to read exactly 4 Bytes of data.
189+
if (region.readBytes(address, 4, Bytes) == -1) {
190+
size = 0;
191+
return MCDisassembler::Fail;
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}
193+
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (Bytes[3] << 0) |
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(Bytes[2] << 8) |
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(Bytes[1] << 16) |
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(Bytes[0] << 24);
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return MCDisassembler::Success;
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}
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DecodeStatus
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SparcDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address,
220+
this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}

‎llvm/lib/Target/Sparc/LLVMBuild.txt

+3-1
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@@ -16,13 +16,15 @@
1616
;===------------------------------------------------------------------------===;
1717

1818
[common]
19-
subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
19+
subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
2020

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[component_0]
2222
type = TargetGroup
2323
name = Sparc
2424
parent = Target
25+
has_asmparser = 1
2526
has_asmprinter = 1
27+
has_disassembler = 1
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has_jit = 1
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[component_1]

‎llvm/lib/Target/Sparc/Makefile

+2-2
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@@ -14,11 +14,11 @@ TARGET = Sparc
1414
# Make sure that tblgen is run, first thing.
1515
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
1616
SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
17-
SparcGenDAGISel.inc \
17+
SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \
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SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
1919
SparcGenCodeEmitter.inc SparcGenMCCodeEmitter.inc
2020

21-
DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
21+
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
2222

2323
include $(LEVEL)/Makefile.common
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