[mips] The naming convention for private labels is ABI dependant.

[dsanders]

Summary

For N32/N64, private labels begin with '.L' but for O32 they begin with '$'.

MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax.

[vkalintiris]

Won't we have to update the existing tests that depend on this behaviour?
I'm getting the following failures with llvm-lit:

Failing Tests (12):

LLVM :: CodeGen/Mips/analyzebranch.ll
LLVM :: CodeGen/Mips/atomic.ll
LLVM :: CodeGen/Mips/blez_bgez.ll
LLVM :: CodeGen/Mips/blockaddr.ll
LLVM :: CodeGen/Mips/fpbr.ll
LLVM :: CodeGen/Mips/llvm-ir/ashr.ll
LLVM :: CodeGen/Mips/llvm-ir/indirectbr.ll
LLVM :: CodeGen/Mips/llvm-ir/lshr.ll
LLVM :: CodeGen/Mips/llvm-ir/select.ll
LLVM :: CodeGen/Mips/llvm-ir/shl.ll
LLVM :: CodeGen/Mips/longbranch.ll
LLVM :: CodeGen/Mips/octeon.ll

Other than that it looks good to me. Please, update the existing revision if you'd like me to review the tests' changes too.

[dsanders]

Now uses the ABI instead of misusing target triples. This required the addition
of an overridable initialization function in MCAsmInfo which provides the ABI
(from the TargetMachine).

Also updated tests.

[vkalintiris]

LGTM.

include/llvm/MC/MCAsmInfo.h

 #include <vector>
 
 namespace llvm {
 class MCExpr;
 class MCSection;
 class MCStreamer;
 class MCSymbol;
 class MCContext;
+class LLVMTargetMachine;
 
 namespace WinEH {
 enum class EncodingType {
   Invalid, /// Invalid
   Alpha,   /// Windows Alpha
   Alpha64, /// Windows AXP64
   ARM,     /// Windows NT (Windows on ARM)
   CE,      /// Windows CE ARM, PowerPC, SH3, SH4
public:
 
   bool compressDebugSections() const { return CompressDebugSections; }
 
   void setCompressDebugSections(bool CompressDebugSections) {
     this->CompressDebugSections = CompressDebugSections;
   }
 
   bool shouldUseLogicalShr() const { return UseLogicalShr; }
+
+  /// Finish initialization of this object. Few targets will need to use this
+  /// but it's useful when the assembly syntax is ABI dependant as is the case
+  /// for Mips.
+  virtual void finishInit(const LLVMTargetMachine &) {}
 };
 }
 
 #endif

lib/CodeGen/LLVMTargetMachine.cpp

assert(TmpAsmInfo && "MCAsmInfo not initialized. "
          "and that InitializeAllTargetMCs() is being invoked!");
 
   if (Options.DisableIntegratedAS)
     TmpAsmInfo->setUseIntegratedAssembler(false);
 
   if (Options.CompressDebugSections)
     TmpAsmInfo->setCompressDebugSections(true);
 
+  TmpAsmInfo->finishInit(*this);
   AsmInfo = TmpAsmInfo;
 }
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
                                      StringRef DataLayoutString,
                                      StringRef Triple, StringRef CPU,
                                      StringRef FS, TargetOptions Options,
                                      Reloc::Model RM, CodeModel::Model CM,

lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

public:
   unsigned GetStackPtr() const;
   unsigned GetFramePtr() const;
   unsigned GetNullPtr() const;
   unsigned GetPtrAdduOp() const;
   unsigned GetPtrAddiuOp() const;
   inline bool ArePtrs64bit() const { return IsN64(); }
 
   unsigned GetEhDataReg(unsigned I) const;
+
+  const char *GetPrivateLabelPrefix() const;
 };
 }
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
   };
   static const unsigned EhDataReg64[] = {
     Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
   };
 
   return IsN64() ? EhDataReg64[I] : EhDataReg[I];
 }
 
+const char *MipsABIInfo::GetPrivateLabelPrefix() const {
+  return IsO32() ? "$" : ".L";
+}

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h

 
 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H
 
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
   class StringRef;
+  class MipsABIInfo;
+  class LLVMTargetMachine;
 
   class MipsMCAsmInfo : public MCAsmInfoELF {
     void anchor() override;
   public:
     explicit MipsMCAsmInfo(StringRef TT);
+
+    void finishInit(const LLVMTargetMachine &TM) override;
   };
 
 } // namespace llvm
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

 //===-- MipsMCAsmInfo.cpp - Mips Asm Properties ---------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the MipsMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCAsmInfo.h"
+#include "MCTargetDesc/MipsABIInfo.h"
+#include "MipsTargetMachine.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 
 void MipsMCAsmInfo::anchor() { }
 
 MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) {
   Triple TheTriple(TT);
   if ((TheTriple.getArch() == Triple::mips) ||
       (TheTriple.getArch() == Triple::mips64))
     IsLittleEndian = false;
 
   if ((TheTriple.getArch() == Triple::mips64el) ||
       (TheTriple.getArch() == Triple::mips64)) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
 
+  // These two are overridden in finishInit()
+  PrivateGlobalPrefix = "$";
+  PrivateLabelPrefix  = "$";
+
   AlignmentIsInBytes          = false;
   Data16bitsDirective         = "\t.2byte\t";
   Data32bitsDirective         = "\t.4byte\t";
   Data64bitsDirective         = "\t.8byte\t";
-  PrivateGlobalPrefix         = "$";
-  PrivateLabelPrefix          = "$";
   CommentString               = "#";
   ZeroDirective               = "\t.space\t";
   GPRel32Directive            = "\t.gpword\t";
   GPRel64Directive            = "\t.gpdword\t";
   UseAssignmentForEHBegin = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   DwarfRegNumForCFI = true;
 }
+
+void MipsMCAsmInfo::finishInit(const LLVMTargetMachine &TM) {
+  const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
+  PrivateGlobalPrefix = ABI.GetPrivateLabelPrefix();
+  PrivateLabelPrefix  = ABI.GetPrivateLabelPrefix();
+}

lib/Target/Mips/MipsTargetMachine.cpp

 #include "Mips16InstrInfo.h"
 #include "MipsFrameLowering.h"
 #include "MipsInstrInfo.h"
 #include "MipsSEFrameLowering.h"
 #include "MipsSEISelDAGToDAG.h"
 #include "MipsSEISelLowering.h"
 #include "MipsSEInstrInfo.h"
 #include "MipsTargetObjectFile.h"
+#include "MCTargetDesc/MipsMCAsmInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Scalar.h"
 

test/CodeGen/Mips/analyzebranch.ll

 ; RUN: llc -march=mips -mcpu=mips32   < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
 ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
 ; RUN: llc -march=mips64 -mcpu=mips4    < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
 ; RUN: llc -march=mips64 -mcpu=mips64   < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
 ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC
 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
 
 define double @foo(double %a, double %b) nounwind readnone {
 entry:
 ; ALL-LABEL: foo:
 
-; FCC:           bc1f $BB
+; FCC:           bc1f {{(\$|.L)BB}}
 ; FCC:           nop
 
 ; 32-GPR:        mtc1      $zero, $[[Z:f[0-9]]]
 ; 32-GPR:        mthc1     $zero, $[[Z:f[0-9]]]
 ; 64-GPR:        dmtc1     $zero, $[[Z:f[0-9]]]
 ; GPR:           cmp.lt.d  $[[FGRCC:f[0-9]+]], $[[Z]], $f12
 ; GPR:           mfc1      $[[GPRCC:[0-9]+]], $[[FGRCC]]
 ; GPR-NOT:       not       $[[GPRCC]], $[[GPRCC]]
-; GPR:           bnez      $[[GPRCC]], $BB
+; GPR:           bnez      $[[GPRCC]], {{(\$|.L)BB}}
 
   %cmp = fcmp ogt double %a, 0.000000e+00
   br i1 %cmp, label %if.end6, label %if.else
 
 if.else:                                          ; preds = %entry
   %cmp3 = fcmp ogt double %b, 0.000000e+00
   br i1 %cmp3, label %if.end6, label %return
 
 if.end6:                                          ; preds = %if.else, %entry
   %c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ]
   %sub = fsub double %b, %c.0
   %mul = fmul double %sub, 2.000000e+00
   br label %return
 
 return:                                           ; preds = %if.else, %if.end6
   %retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ]
   ret double %retval.0
 }
 
 define void @f1(float %f) nounwind {
 entry:
 ; ALL-LABEL: f1:
 
-; FCC:           bc1f $BB
+; FCC:           bc1f {{(\$|.L)BB}}
 ; FCC:           nop
 
 ; GPR:           mtc1     $zero, $[[Z:f[0-9]]]
 ; GPR:           cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]]
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC]]
 ; GPR-NOT:       not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           beqz     $[[GPRCC]], $BB
+; GPR:           beqz     $[[GPRCC]], {{(\$|.L)BB}}
 
   %cmp = fcmp une float %f, 0.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   tail call void @abort() noreturn
   unreachable
 
 if.end:                                           ; preds = %entry
   tail call void (...) @f2() nounwind
   ret void
 }
 
 declare void @abort() noreturn nounwind
 
 declare void @f2(...)

test/CodeGen/Mips/atomic.ll

entry:
   %0 = atomicrmw add i32* @x, i32 %incr monotonic
   ret i32 %0
 
 ; ALL-LABEL: AtomicLoadAdd32:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; ALL:           sc      $[[R2]], 0($[[R0]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R2]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R2]], [[BB0]]
 }
 
 define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
 entry:
   %0 = atomicrmw nand i32* @x, i32 %incr monotonic
   ret i32 %0
 
 ; ALL-LABEL: AtomicLoadNand32:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; ALL:           and     $[[R3:[0-9]+]], $[[R1]], $4
 ; ALL:           nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; ALL:           sc      $[[R2]], 0($[[R0]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R2]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R2]], [[BB0]]
 }
 
 define i32 @AtomicSwap32(i32 signext %newval) nounwind {
 entry:
   %newval.addr = alloca i32, align 4
   store i32 %newval, i32* %newval.addr, align 4
   %tmp = load i32, i32* %newval.addr, align 4
   %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
   ret i32 %0
 
 ; ALL-LABEL: AtomicSwap32:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      ${{[0-9]+}}, 0($[[R0]])
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R2]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R2]], [[BB0]]
 }
 
 define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
 entry:
   %newval.addr = alloca i32, align 4
   store i32 %newval, i32* %newval.addr, align 4
   %tmp = load i32, i32* %newval.addr, align 4
   %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
   %1 = extractvalue { i32, i1 } %0, 0
   ret i32 %1
 
 ; ALL-LABEL: AtomicCmpSwap32:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $2, 0($[[R0]])
-; ALL:           bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
+; ALL:           bne     $2, $4, [[BB1:(\$|.L)[A-Z_0-9]+]]
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
-; ALL:       $[[BB1]]:
+; NOT-MICROMIPS: beqz    $[[R2]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R2]], [[BB0]]
+; ALL:       [[BB1]]:
 }
 
 
 
 @y = common global i8 0, align 1
 
 define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
 entry:

 ; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
 ; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
 ; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
 ; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
 ; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R14]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R14]], [[BB0]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]

 ; CHECK-EL:   sll     $[[R5:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:   xori    $[[R4:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:   sll     $[[R5:[0-9]+]], $[[R4]], 3
 ; ALL:        ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:        sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:        nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:        sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
-; ALL:    $[[BB0:[A-Z_0-9]+]]:
+; ALL:    [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:        ll      $[[R10:[0-9]+]], 0($[[R2]])
 ; ALL:        subu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
 ; ALL:        and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
 ; ALL:        and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; ALL:        or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; ALL:        sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:  beqzc   $[[R14]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R14]], [[BB0]]
+; MICROMIPS:  beqzc   $[[R14]], [[BB0]]
 
 ; ALL:        and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:        srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH: sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH: sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:seb     $2, $[[R16]]

 ; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R18:[0-9]+]], $[[R10]], $[[R9]]
 ; ALL:           nor     $[[R11:[0-9]+]], $zero, $[[R18]]
 ; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
 ; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R14]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R14]], [[BB0]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]

 ; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
 ; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R18:[0-9]+]], $[[R9]], $[[R7]]
 ; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
 ; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R14]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R14]], [[BB0]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]

 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           andi    $[[R9:[0-9]+]], $4, 255
 ; ALL:           sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
 ; ALL:           andi    $[[R11:[0-9]+]], $5, 255
 ; ALL:           sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
-; ALL:           bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; ALL:           bne     $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; ALL:           sc      $[[R16]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R16]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R16]], [[BB0]]
 
-; ALL:       $[[BB1]]:
+; ALL:       [[BB1]]:
 ; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R18]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R17]]
 }
 

 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           andi    $[[R9:[0-9]+]], $5, 255
 ; ALL:           sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
 ; ALL:           andi    $[[R11:[0-9]+]], $6, 255
 ; ALL:           sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
-; ALL:           bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; ALL:           bne     $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; ALL:           sc      $[[R16]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R16]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R16]], [[BB0]]
 
-; ALL:       $[[BB1]]:
+; ALL:       [[BB1]]:
 ; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
 ; NO-SEB-SEH:    sra     $[[R19:[0-9]+]], $[[R18]], 24
 
 ; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
 
 ; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5

 ; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 2
 ; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
 ; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
 ; ALL:           ori     $[[R6:[0-9]+]], $zero, 65535
 ; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
 ; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
 ; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
 ; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R14]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R14]], [[BB0]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 16
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 16
 
 ; MIPS32R2:      seh     $2, $[[R16]]
entry:
   ret i32 %0
 
 ; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
 ; ALL:           addiu   $[[PTR:[0-9]+]], $[[R0]], 1024
-; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:       [[BB0:(\$|.L)[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R1:[0-9]+]], 0($[[PTR]])
 ; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; ALL:           sc      $[[R2]], 0($[[PTR]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; NOT-MICROMIPS: beqz    $[[R2]], [[BB0]]
+; MICROMIPS:     beqzc   $[[R2]], [[BB0]]
 }

test/CodeGen/Mips/blez_bgez.ll

 ; RUN: llc -march=mipsel < %s | FileCheck %s
 ; RUN: llc -march=mips64el < %s | FileCheck %s
 
 ; CHECK-LABEL: test_blez:
-; CHECK: blez ${{[0-9]+}}, $BB
+; CHECK: blez ${{[0-9]+}}, {{(\$|.L)BB}}
 
 define void @test_blez(i32 %a) {
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @foo1()
   br label %if.end
 
 if.end:
   ret void
 }
 
 declare void @foo1()
 
 ; CHECK-LABEL: test_bgez:
-; CHECK: bgez ${{[0-9]+}}, $BB
+; CHECK: bgez ${{[0-9]+}}, {{(\$|.L)BB}}
 
 define void @test_bgez(i32 %a) {
 entry:
   %cmp = icmp slt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   tail call void @foo1()
   br label %if.end
 
 if.end:
   ret void
 }

test/CodeGen/Mips/blockaddr.ll

 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-1
 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-2
 
 @reg = common global i8* null, align 4
 
 define i8* @dummy(i8* %x) nounwind readnone noinline {
 entry:
   ret i8* %x
 }
 
-; PIC-O32: lw  $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])
-; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
-; PIC-O32: lw  $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])
-; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
-; STATIC-O32: lui  $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
-; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
-; STATIC-O32: lui   $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
-; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
-; PIC-N32: lw  $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
-; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
-; PIC-N32: lw  $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
-; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
-; STATIC-N32: lui  $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
-; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
-; STATIC-N32: lui   $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
-; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
-; PIC-N64: ld  $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
-; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
-; PIC-N64: ld  $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
-; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
-; STATIC-N64: ld  $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]])
-; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]])
-; STATIC-N64: ld  $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]])
-; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]])
+; PIC-O32: lw  $[[R0:[0-9]+]], %got([[T0:(\$|.L)tmp[0-9]+]])
+; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo([[T0]])
+; PIC-O32: lw  $[[R1:[0-9]+]], %got([[T1:(\$|.L)tmp[0-9]+]])
+; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo([[T1]])
+; STATIC-O32: lui  $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]])
+; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]])
+; STATIC-O32: lui   $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]])
+; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]])
+; PIC-N32: lw  $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]])
+; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]])
+; PIC-N32: lw  $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]])
+; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]])
+; STATIC-N32: lui  $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]])
+; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]])
+; STATIC-N32: lui   $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]])
+; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]])
+; PIC-N64: ld  $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]])
+; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]])
+; PIC-N64: ld  $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]])
+; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]])
+; STATIC-N64: ld  $[[R2:[0-9]+]], %got_page([[T2:(\$|.L)tmp[0-9]+]])
+; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst([[T2]])
+; STATIC-N64: ld  $[[R3:[0-9]+]], %got_page([[T3:(\$|.L)tmp[0-9]+]])
+; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst([[T3]])
 ; STATIC-MIPS16-1: .ent f
 ; STATIC-MIPS16-2: .ent f
 ; STATIC-MIPS16-1: li  $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
 ; STATIC-MIPS16-1: sll ${{[0-9]+}},  $[[R1_16]], 16
 ; STATIC-MIPS16-2: li  ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
 ; STATIC-MIPS16-1: jal  dummy
 ; STATIC-MIPS16-2: jal  dummy
 

test/CodeGen/Mips/fpbr.ll

 ; RUN: llc < %s -march=mipsel -mcpu=mips32   | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
 ; RUN: llc < %s -march=mips64el -mcpu=mips64   | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC
 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
 
 define void @func0(float %f2, float %f3) nounwind {
 entry:
 ; ALL-LABEL: func0:
 
 ; 32-FCC:        c.eq.s $f12, $f14
 ; 64-FCC:        c.eq.s $f12, $f13
-; FCC:           bc1f   $BB0_2
+; FCC:           bc1f   {{(\$|.L)BB0_2}}
 
 ; 32-GPR:        cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
 ; 64-GPR:        cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; FIXME: We ought to be able to transform not+bnez -> beqz
 ; GPR:           not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           bnez     $[[GPRCC]], $BB0_2
+; GPR:           bnez     $[[GPRCC]], {{(\$|.L)BB0_2}}
 
   %cmp = fcmp oeq float %f2, %f3
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 

 declare void @g1(...)
 
 define void @func1(float %f2, float %f3) nounwind {
 entry:
 ; ALL-LABEL: func1:
 
 ; 32-FCC:        c.olt.s $f12, $f14
 ; 64-FCC:        c.olt.s $f12, $f13
-; FCC:           bc1f    $BB1_2
+; FCC:           bc1f    {{(\$|.L)BB1_2}}
 
 ; 32-GPR:        cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
 ; 64-GPR:        cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; GPR-NOT:       not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           bnez     $[[GPRCC]], $BB1_2
+; GPR:           bnez     $[[GPRCC]], {{(\$|.L)BB1_2}}
 
   %cmp = fcmp olt float %f2, %f3
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   ret void
 }
 
 define void @func2(float %f2, float %f3) nounwind {
 entry:
 ; ALL-LABEL: func2:
 
 ; 32-FCC:        c.ole.s $f12, $f14
 ; 64-FCC:        c.ole.s $f12, $f13
-; FCC:           bc1t    $BB2_2
+; FCC:           bc1t    {{(\$|.L)BB2_2}}
 
 ; 32-GPR:        cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
 ; 64-GPR:        cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; GPR-NOT:       not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           beqz     $[[GPRCC]], $BB2_2
+; GPR:           beqz     $[[GPRCC]], {{(\$|.L)BB2_2}}
 
   %cmp = fcmp ugt float %f2, %f3
   br i1 %cmp, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   ret void
 }
 
 define void @func3(double %f2, double %f3) nounwind {
 entry:
 ; ALL-LABEL: func3:
 
 ; 32-FCC:        c.eq.d $f12, $f14
 ; 64-FCC:        c.eq.d $f12, $f13
-; FCC:           bc1f $BB3_2
+; FCC:           bc1f {{(\$|.L)BB3_2}}
 
 ; 32-GPR:        cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
 ; 64-GPR:        cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; FIXME: We ought to be able to transform not+bnez -> beqz
 ; GPR:           not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           bnez     $[[GPRCC]], $BB3_2
+; GPR:           bnez     $[[GPRCC]], {{(\$|.L)BB3_2}}
 
   %cmp = fcmp oeq double %f2, %f3
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   ret void
 }
 
 define void @func4(double %f2, double %f3) nounwind {
 entry:
 ; ALL-LABEL: func4:
 
 ; 32-FCC:        c.olt.d $f12, $f14
 ; 64-FCC:        c.olt.d $f12, $f13
-; FCC:           bc1f $BB4_2
+; FCC:           bc1f {{(\$|.L)BB4_2}}
 
 ; 32-GPR:        cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
 ; 64-GPR:        cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; GPR-NOT:       not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           bnez     $[[GPRCC]], $BB4_2
+; GPR:           bnez     $[[GPRCC]], {{(\$|.L)BB4_2}}
 
   %cmp = fcmp olt double %f2, %f3
   br i1 %cmp, label %if.then, label %if.else
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   ret void
 }
 
 define void @func5(double %f2, double %f3) nounwind {
 entry:
 ; ALL-LABEL: func5:
 
 ; 32-FCC:        c.ole.d $f12, $f14
 ; 64-FCC:        c.ole.d $f12, $f13
-; FCC:           bc1t $BB5_2
+; FCC:           bc1t {{(\$|.L)BB5_2}}
 
 ; 32-GPR:        cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
 ; 64-GPR:        cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
 ; GPR:           mfc1     $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
 ; GPR-NOT:       not      $[[GPRCC]], $[[GPRCC]]
-; GPR:           beqz     $[[GPRCC]], $BB5_2
+; GPR:           beqz     $[[GPRCC]], {{(\$|.L)BB5_2}}
 
   %cmp = fcmp ugt double %f2, %f3
   br i1 %cmp, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry
   tail call void (...) @g0() nounwind
   br label %if.end
 
 if.else:                                          ; preds = %entry
   tail call void (...) @g1() nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %if.then
   ret void
 }

test/CodeGen/Mips/llvm-ir/ashr.ll

 }
 
 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i64:
 
   ; M2:         srav      $[[T0:[0-9]+]], $4, $7
   ; M2:         andi      $[[T1:[0-9]+]], $7, 32
-  ; M2:         bnez      $[[T1]], $[[BB0:BB[0-9_]+]]
+  ; M2:         bnez      $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2:         move      $3, $[[T0]]
   ; M2:         srlv      $[[T2:[0-9]+]], $5, $7
   ; M2:         not       $[[T3:[0-9]+]], $7
   ; M2:         sll       $[[T4:[0-9]+]], $4, 1
   ; M2:         sllv      $[[T5:[0-9]+]], $[[T4]], $[[T3]]
   ; M2:         or        $3, $[[T3]], $[[T2]]
-  ; M2:         $[[BB0]]:
-  ; M2:         beqz      $[[T1]], $[[BB1:BB[0-9_]+]]
+  ; M2:         [[BB0]]:
+  ; M2:         beqz      $[[T1]], [[BB1:(\$|.L)BB[0-9_]+]]
   ; M2:         nop
   ; M2:         sra       $2, $4, 31
-  ; M2:         $[[BB1]]:
+  ; M2:         [[BB1]]:
   ; M2:         jr        $ra
   ; M2:         nop
 
   ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
   ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
   ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
   ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]

 entry:
 ; ALL-LABEL: ashr_i128:
 
   ; GP32:           lw        $25, %call16(__ashrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
-  ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
+  ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
   ; M3:             or        $3, $[[T7]], $[[T4]]
-  ; M3:             $[[BB0]]:
-  ; M3:             beqz      $[[T3]], $[[BB1:BB[0-9_]+]]
+  ; M3:             [[BB0]]:
+  ; M3:             beqz      $[[T3]], [[BB1:(\$|.L)BB[0-9_]+]]
   ; M3:             nop
   ; M3:             dsra      $2, $4, 63
-  ; M3:             $[[BB1]]:
+  ; M3:             [[BB1]]:
   ; M3:             jr        $ra
   ; M3:             nop
 
   ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
   ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
   ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
   ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
   ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]

test/CodeGen/Mips/llvm-ir/indirectbr.ll

 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 
 define i32 @br(i8 *%addr) {
 ; ALL-LABEL: br:
 ; NOT-R6:        jr $4 # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $4 # <MCInst #{{[0-9]+}} JALR
 
-; ALL: $BB0_1: # %L1
+; ALL: {{(\$|.L)BB0_1}}: # %L1
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 0
 
-; ALL: $BB0_2: # %L2
+; ALL: {{(\$|.L)BB0_2}}: # %L2
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 1
 
 entry:
   indirectbr i8* %addr, [label %L1, label %L2]
 
 L1:
   ret i32 0
 
 L2:
   ret i32 1
 }

test/CodeGen/Mips/llvm-ir/lshr.ll

 entry:
 ; ALL-LABEL: lshr_i128:
 
   ; GP32:         lw      $25, %call16(__lshrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
-  ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
+  ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:($|.L)BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
   ; M3:             or        $3, $[[T7]], $[[T4]]
-  ; M3:             $[[BB0]]:
-  ; M3:             bnez      $[[T3]], $[[BB1:BB[0-9_]+]]
+  ; M3:             [[BB0]]:
+  ; M3:             bnez      $[[T3]], [[BB1:($|.L)BB[0-9_]+]]
   ; M3:             daddiu    $2, $zero, 0
   ; M3:             move      $2, $[[T1]]
-  ; M3:             $[[BB1]]:
+  ; M3:             [[BB1]]:
   ; M3:             jr        $ra
   ; M3:             nop
 
   ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
   ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
   ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
   ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
   ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]

test/CodeGen/Mips/llvm-ir/select.ll

 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
 define signext i1 @tst_select_i1_i1(i1 signext %s,
                                     i1 signext %x, i1 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i1:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:  bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
+  ; M2-M3:  [[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i1 %x, i1 %y
   ret i1 %r
 }
 
 define signext i8 @tst_select_i1_i8(i1 signext %s,
                                     i8 signext %x, i8 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i8:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:  bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
+  ; M2-M3:  [[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i8 %x, i8 %y
   ret i8 %r
 }
 
 define signext i32 @tst_select_i1_i32(i1 signext %s,
                                       i32 signext %x, i32 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i32:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:  bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
+  ; M2-M3:  [[BB0]]:
   ; M2-M3:  jr      $ra
   ; M2-M3:  move    $2, $5
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
   ; CMOV:   move    $2, $6
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
   ; SEL:    or      $2, $[[T2]], $[[T1]]
   %r = select i1 %s, i32 %x, i32 %y
   ret i32 %r
 }
 
 define signext i64 @tst_select_i1_i64(i1 signext %s,
                                       i64 signext %x, i64 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i64:
 
   ; M2:     andi    $[[T0:[0-9]+]], $4, 1
-  ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:     bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2:     nop
   ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
-  ; M2:     $[[BB0]]:
+  ; M2:     [[BB0]]:
   ; FIXME: This branch is redundant
   ; M2:     bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
   ; M2:     nop
   ; M2:     lw      $[[T2:[0-9]+]], 20($sp)
   ; M2:     $[[BB1]]:
   ; M2:     move    $2, $[[T1]]
   ; M2:     jr      $ra
   ; M2:     move    $3, $[[T2]]
entry:
   ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
   ; SEL-32:     or      $2, $[[T1]], $[[T3]]
   ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
   ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
   ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
   ; SEL-32:     or      $3, $[[T4]], $[[T6]]
 
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
-  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M3:         nop
   ; M3:         move    $5, $6
-  ; M3:         $[[BB0]]:
+  ; M3:         [[BB0]]:
   ; M3:         jr      $ra
   ; M3:         move    $2, $5
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn    $6, $5, $[[T0]]
   ; CMOV-64:    move    $2, $6
 
   ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
   ; FIXME: This shift is redundant
   ; SEL-64:     sll     $[[T0]], $[[T0]], 0
   ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
   ; SEL-64:     or      $2, $[[T0]], $[[T1]]
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }
 
 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_float:
 
   ; M2-M3:      andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f0
   ; M3:         mov.s   $f13, $f14
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr      $ra
   ; M2:         mtc1    $5, $f0
   ; M3:         mov.s   $f0, $f13
 
   ; CMOV-32:    mtc1    $6, $f0
   ; CMOV-32:    mtc1    $5, $f1
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]

 }
 
 define float @tst_select_i1_float_reordered(float %x, float %y,
                                             i1 signext %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_float_reordered:
 
   ; M2-M3:      andi    $[[T0:[0-9]+]], $6, 1
-  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s   $f12, $f14
   ; M3:         mov.s   $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr      $ra
   ; M2-M3:      mov.s   $f0, $f12
 
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
   ; CMOV-32:    mov.s   $f0, $f14
 
   ; SEL-32:     mtc1    $6, $f0
entry:
   ret float %r
 }
 
 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_double:
 
   ; M2:         andi    $[[T0:[0-9]+]], $4, 1
-  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2:         nop
   ; M2:         ldc1    $f0, 16($sp)
   ; M2:         jr      $ra
   ; M2:         nop
-  ; M2:         $[[BB0]]:
+  ; M2:         [[BB0]]:
   ; M2:         mtc1    $7, $f0
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f1
 
   ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
   ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
   ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
   ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-32:      ldc1    $f0, 16($sp)
   ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
 
   ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
   ; SEL-32:     mthc1   $6, $[[F0]]
   ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
   ; SEL-32:     mtc1    $4, $f0
   ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
 
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
-  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M3:         nop
   ; M3:         mov.d   $f13, $f14
-  ; M3:         $[[BB0]]:
+  ; M3:         [[BB0]]:
   ; M3:         jr      $ra
   ; M3:         mov.d   $f0, $f13
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f14
 
   ; SEL-64:     mtc1    $4, $f0
   ; SEL-64:     sel.d   $f0, $f14, $f13
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_i1_double_reordered(double %x, double %y,
                                               i1 signext %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_double_reordered:
 
   ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
   ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
-  ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
+  ; M2:         bnez    $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2:         nop
   ; M2:         mov.d   $f12, $f14
-  ; M2:         $[[BB0]]:
+  ; M2:         [[BB0]]:
   ; M2:         jr      $ra
   ; M2:         mov.d   $f0, $f12
 
   ; CMOV-32:    lw      $[[T0:[0-9]+]], 16($sp)
   ; CMOV-32:    andi    $[[T1:[0-9]+]], $[[T0]], 1
   ; CMOV-32:    movn.d  $f14, $f12, $[[T1]]
   ; CMOV-32:    mov.d   $f0, $f14
 
   ; SEL-32:     lw      $[[T0:[0-9]+]], 16($sp)
   ; SEL-32:     mtc1    $[[T0]], $f0
   ; SEL-32:     sel.d   $f0, $f14, $f12
 
   ; M3:         andi    $[[T0:[0-9]+]], $6, 1
-  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         bnez    $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M3:         nop
   ; M3:         mov.d   $f12, $f13
-  ; M3:         $[[BB0]]:
+  ; M3:         [[BB0]]:
   ; M3:         jr      $ra
   ; M3:         mov.d   $f0, $f12
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f13
 
   ; SEL-64:     mtc1    $6, $f0
   ; SEL-64:     sel.d   $f0, $f13, $f12
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define float @tst_select_fcmp_olt_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_float:
 
   ; M2:         c.olt.s   $f12, $f14
   ; M3:         c.olt.s   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.olt.s   $f12, $f14
   ; CMOV-32:    movt.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.lt.s  $f0, $f12, $f14

 }
 
 define float @tst_select_fcmp_ole_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ole_float:
 
   ; M2:         c.ole.s   $f12, $f14
   ; M3:         c.ole.s   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.ole.s   $f12, $f14
   ; CMOV-32:    movt.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.le.s  $f0, $f12, $f14

 }
 
 define float @tst_select_fcmp_ogt_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ogt_float:
 
   ; M2:         c.ule.s   $f12, $f14
   ; M3:         c.ule.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.ule.s   $f12, $f14
   ; CMOV-32:    movf.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.lt.s  $f0, $f14, $f12

 }
 
 define float @tst_select_fcmp_oge_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oge_float:
 
   ; M2:         c.ult.s   $f12, $f14
   ; M3:         c.ult.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.ult.s   $f12, $f14
   ; CMOV-32:    movf.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.le.s  $f0, $f14, $f12

 }
 
 define float @tst_select_fcmp_oeq_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oeq_float:
 
   ; M2:         c.eq.s    $f12, $f14
   ; M3:         c.eq.s    $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.eq.s    $f12, $f14
   ; CMOV-32:    movt.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.eq.s  $f0, $f12, $f14

 }
 
 define float @tst_select_fcmp_one_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_one_float:
 
   ; M2:         c.ueq.s   $f12, $f14
   ; M3:         c.ueq.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.s     $f12, $f14
   ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.s     $f0, $f12
 
   ; CMOV-32:    c.ueq.s   $f12, $f14
   ; CMOV-32:    movf.s    $f14, $f12, $fcc0
   ; CMOV-32:    mov.s     $f0, $f14
 
   ; SEL-32:     cmp.ueq.s $f0, $f12, $f14

 }
 
 define double @tst_select_fcmp_olt_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_double:
 
   ; M2:         c.olt.d   $f12, $f14
   ; M3:         c.olt.d   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.olt.d   $f12, $f14
   ; CMOV-32:    movt.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.lt.d  $f0, $f12, $f14

 }
 
 define double @tst_select_fcmp_ole_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ole_double:
 
   ; M2:         c.ole.d   $f12, $f14
   ; M3:         c.ole.d   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.ole.d   $f12, $f14
   ; CMOV-32:    movt.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.le.d  $f0, $f12, $f14

 }
 
 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ogt_double:
 
   ; M2:         c.ule.d   $f12, $f14
   ; M3:         c.ule.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.ule.d   $f12, $f14
   ; CMOV-32:    movf.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.lt.d  $f0, $f14, $f12

 }
 
 define double @tst_select_fcmp_oge_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oge_double:
 
   ; M2:         c.ult.d   $f12, $f14
   ; M3:         c.ult.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.ult.d   $f12, $f14
   ; CMOV-32:    movf.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.le.d  $f0, $f14, $f12

 }
 
 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oeq_double:
 
   ; M2:         c.eq.d    $f12, $f14
   ; M3:         c.eq.d    $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1t      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.eq.d    $f12, $f14
   ; CMOV-32:    movt.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.eq.d  $f0, $f12, $f14

 }
 
 define double @tst_select_fcmp_one_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_one_double:
 
   ; M2:         c.ueq.d   $f12, $f14
   ; M3:         c.ueq.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:      bc1f      [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2-M3:      nop
   ; M2:         mov.d     $f12, $f14
   ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
+  ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr        $ra
   ; M2-M3:      mov.d     $f0, $f12
 
   ; CMOV-32:    c.ueq.d   $f12, $f14
   ; CMOV-32:    movf.d    $f14, $f12, $fcc0
   ; CMOV-32:    mov.d     $f0, $f14
 
   ; SEL-32:     cmp.ueq.d $f0, $f12, $f14

test/CodeGen/Mips/llvm-ir/shl.ll

 }
 
 define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: shl_i64:
 
   ; M2:         sllv      $[[T0:[0-9]+]], $5, $7
   ; M2:         andi      $[[T1:[0-9]+]], $7, 32
-  ; M2:         bnez      $[[T1]], $[[BB0:BB[0-9_]+]]
+  ; M2:         bnez      $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M2:         move      $2, $[[T0]]
   ; M2:         sllv      $[[T2:[0-9]+]], $4, $7
   ; M2:         not       $[[T3:[0-9]+]], $7
   ; M2:         srl       $[[T4:[0-9]+]], $5, 1
   ; M2:         srlv      $[[T5:[0-9]+]], $[[T4]], $[[T3]]
   ; M2:         or        $2, $[[T2]], $[[T3]]
-  ; M2:         $[[BB0]]:
-  ; M2:         bnez      $[[T1]], $[[BB1:BB[0-9_]+]]
+  ; M2:         [[BB0]]:
+  ; M2:         bnez      $[[T1]], [[BB1:(\$|.L)BB[0-9_]+]]
   ; M2:         addiu     $3, $zero, 0
   ; M2:         move      $3, $[[T0]]
-  ; M2:         $[[BB1]]:
+  ; M2:         [[BB1]]:
   ; M2:         jr        $ra
   ; M2:         nop
 
   ; 32R1-R5:    sllv      $[[T0:[0-9]+]], $4, $7
   ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
   ; 32R1-R5:    srl       $[[T2:[0-9]+]], $5, 1
   ; 32R1-R5:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 32R1-R5:    or        $2, $[[T0]], $[[T3]]

 entry:
 ; ALL-LABEL: shl_i128:
 
   ; GP32:           lw        $25, %call16(__ashlti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
-  ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
+  ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:(\$|.L)BB[0-9_]+]]
   ; M3:             move      $2, $[[T1]]
   ; M3:             dsllv     $[[T4:[0-9]+]], $4, $7
   ; M3:             dsrl      $[[T5:[0-9]+]], $5, 1
   ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
   ; M3:             dsrlv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
   ; M3:             or        $2, $[[T4]], $[[T7]]
-  ; M3:             $[[BB0]]:
-  ; M3:             bnez      $[[T3]], $[[BB1:BB[0-9_]+]]
+  ; M3:             [[BB0]]:
+  ; M3:             bnez      $[[T3]], [[BB1:(\$|.L)BB[0-9_]+]]
   ; M3:             daddiu    $3, $zero, 0
   ; M3:             move      $3, $[[T1]]
-  ; M3:             $[[BB1]]:
+  ; M3:             [[BB1]]:
   ; M3:             jr        $ra
   ; M3:             nop
 
   ; GP64-NOT-R6:    dsllv     $[[T0:[0-9]+]], $4, $7
   ; GP64-NOT-R6:    dsrl      $[[T1:[0-9]+]], $5, 1
   ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
   ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
   ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]

test/CodeGen/Mips/longbranch.ll

end:
   ret void
 
 
 ; First check the normal version (without long branch).  beqz jumps to return,
 ; and fallthrough block stores 1 to global variable.
 
 ; CHECK:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; CHECK:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
-; CHECK:        beqz    $4, $[[BB0:BB[0-9_]+]]
+; CHECK:        beqz    $4, [[BB0:(\$|.L)BB[0-9_]+]]
 ; CHECK:        addu    $[[GP:[0-9]+]], $[[R0]], $25
 ; CHECK:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; CHECK:        addiu   $[[R2:[0-9]+]], $zero, 1
 ; CHECK:        sw      $[[R2]], 0($[[R1]])
-; CHECK:   $[[BB0]]:
+; CHECK:   [[BB0]]:
 ; CHECK:        jr      $ra
 ; CHECK:        nop
 
 
 ; Check the MIPS32 version.  Check that branch logic is inverted, so that the
 ; target of the new branch (bnez) is the fallthrough block of the original
 ; branch.  Check that fallthrough block of the new branch contains long branch
 ; expansion which at the end indirectly jumps to the target of the original
 ; branch.
 
 ; O32:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; O32:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
-; O32:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; O32:        bnez    $4, [[BB0:(\$|.L)BB[0-9_]+]]
 ; O32:        addu    $[[GP:[0-9]+]], $[[R0]], $25
 
 ; Check for long branch expansion:
 ; O32:             addiu   $sp, $sp, -8
 ; O32-NEXT:        sw      $ra, 0($sp)
-; O32-NEXT:        lui     $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
-; O32-NEXT:        bal     $[[BB1]]
-; O32-NEXT:        addiu   $1, $1, %lo(($[[BB2]])-($[[BB1]]))
-; O32-NEXT:   $[[BB1]]:
+; O32-NEXT:        lui     $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
+; O32-NEXT:        bal     [[BB1]]
+; O32-NEXT:        addiu   $1, $1, %lo(([[BB2]])-([[BB1]]))
+; O32-NEXT:   [[BB1]]:
 ; O32-NEXT:        addu    $1, $ra, $1
 ; O32-NEXT:        lw      $ra, 0($sp)
 ; O32-NEXT:        jr      $1
 ; O32-NEXT:        addiu   $sp, $sp, 8
 
-; O32:   $[[BB0]]:
+; O32:   [[BB0]]:
 ; O32:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; O32:        addiu   $[[R2:[0-9]+]], $zero, 1
 ; O32:        sw      $[[R2]], 0($[[R1]])
-; O32:   $[[BB2]]:
+; O32:   [[BB2]]:
 ; O32:        jr      $ra
 ; O32:        nop
 
 
 ; Check the MIPS64 version.
 
 ; N64:        lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
-; N64:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; N64:        bnez    $4, [[BB0:(\$|.L)BB[0-9_]+]]
 ; N64:        daddu   $[[R1:[0-9]+]], $[[R0]], $25
 
 ; Check for long branch expansion:
 ; N64:           daddiu  $sp, $sp, -16
 ; N64-NEXT:      sd      $ra, 0($sp)
-; N64-NEXT:      daddiu  $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
+; N64-NEXT:      daddiu  $1, $zero, %hi([[BB2:(\$|.L)BB[0-9_]+]]-[[BB1:(\$|.L)BB[0-9_]+]])
 ; N64-NEXT:      dsll    $1, $1, 16
-; N64-NEXT:      bal     $[[BB1]]
-; N64-NEXT:      daddiu  $1, $1, %lo(($[[BB2]])-($[[BB1]]))
-; N64-NEXT:  $[[BB1]]:
+; N64-NEXT:      bal     [[BB1]]
+; N64-NEXT:      daddiu  $1, $1, %lo([[BB2]]-[[BB1]])
+; N64-NEXT:  [[BB1]]:
 ; N64-NEXT:      daddu   $1, $ra, $1
 ; N64-NEXT:      ld      $ra, 0($sp)
 ; N64-NEXT:      jr      $1
 ; N64-NEXT:      daddiu  $sp, $sp, 16
 
-; N64:   $[[BB0]]:
+; N64:   [[BB0]]:
 ; N64:        daddiu  $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
 ; N64:        ld      $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
 ; N64:        addiu   $[[R3:[0-9]+]], $zero, 1
 ; N64:        sw      $[[R3]], 0($[[R2]])
-; N64:   $[[BB2]]:
+; N64:   [[BB2]]:
 ; N64:        jr      $ra
 ; N64:        nop
 
 
 ; Check the microMIPS version.
 
 ; MICROMIPS:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; MICROMIPS:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
-; MICROMIPS:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; MICROMIPS:        bnez    $4, [[BB0:(\$|.L)BB[0-9_]+]]
 ; MICROMIPS:        addu    $[[GP:[0-9]+]], $[[R0]], $25
 
 ; Check for long branch expansion:
 ; MICROMIPS:          addiu   $sp, $sp, -8
 ; MICROMIPS-NEXT:     sw      $ra, 0($sp)
-; MICROMIPS-NEXT:     lui     $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
-; MICROMIPS-NEXT:     bal     $[[BB1]]
-; MICROMIPS-NEXT:     addiu   $1, $1, %lo(($[[BB2]])-($[[BB1]]))
-; MICROMIPS-NEXT:  $[[BB1]]:
+; MICROMIPS-NEXT:     lui     $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
+; MICROMIPS-NEXT:     bal     [[BB1]]
+; MICROMIPS-NEXT:     addiu   $1, $1, %lo(([[BB2]])-([[BB1]]))
+; MICROMIPS-NEXT:  [[BB1]]:
 ; MICROMIPS-NEXT:     addu    $1, $ra, $1
 ; MICROMIPS-NEXT:     lw      $ra, 0($sp)
 ; MICROMIPS-NEXT:     jr      $1
 ; MICROMIPS-NEXT:     addiu   $sp, $sp, 8
 
-; MICROMIPS:   $[[BB0]]:
+; MICROMIPS:   [[BB0]]:
 ; MICROMIPS:        lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; MICROMIPS:        li16    $[[R2:[0-9]+]], 1
 ; MICROMIPS:        sw16    $[[R2]], 0($[[R1]])
-; MICROMIPS:   $[[BB2]]:
+; MICROMIPS:   [[BB2]]:
 ; MICROMIPS:        jrc      $ra
 
 
 ; Check the NaCl version.  Check that sp change is not in the branch delay slot
 ; of "jr $1" instruction.  Check that target of indirect branch "jr $1" is
 ; bundle aligned.
 
 ; NACL:        lui     $[[R0:[0-9]+]], %hi(_gp_disp)
 ; NACL:        addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
-; NACL:        bnez    $4, $[[BB0:BB[0-9_]+]]
+; NACL:        bnez    $4, [[BB0:(\$|.L)BB[0-9_]+]]
 ; NACL:        addu    $[[GP:[0-9]+]], $[[R0]], $25
 
 ; Check for long branch expansion:
 ; NACL:             addiu   $sp, $sp, -8
 ; NACL-NEXT:        sw      $ra, 0($sp)
-; NACL-NEXT:        lui     $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
-; NACL-NEXT:        bal     $[[BB1]]
-; NACL-NEXT:        addiu   $1, $1, %lo(($[[BB2]])-($[[BB1]]))
-; NACL-NEXT:   $[[BB1]]:
+; NACL-NEXT:        lui     $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
+; NACL-NEXT:        bal     [[BB1]]
+; NACL-NEXT:        addiu   $1, $1, %lo(([[BB2]])-([[BB1]]))
+; NACL-NEXT:   [[BB1]]:
 ; NACL-NEXT:        addu    $1, $ra, $1
 ; NACL-NEXT:        lw      $ra, 0($sp)
 ; NACL-NEXT:        addiu   $sp, $sp, 8
 ; NACL-NEXT:        jr      $1
 ; NACL-NEXT:        nop
 
-; NACL:        $[[BB0]]:
+; NACL:        [[BB0]]:
 ; NACL:             lw      $[[R1:[0-9]+]], %got(x)($[[GP]])
 ; NACL:             addiu   $[[R2:[0-9]+]], $zero, 1
 ; NACL:             sw      $[[R2]], 0($[[R1]])
 ; NACL:             .align  4
-; NACL-NEXT:   $[[BB2]]:
+; NACL-NEXT:   [[BB2]]:
 ; NACL:             jr      $ra
 ; NACL:             nop
 }

test/CodeGen/Mips/octeon.ll

; MIPS64: dsrl   $2, $[[T3]], 32
   %res = icmp ne i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
 define i64 @bbit0(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: bbit0:
-; OCTEON: bbit0   $4, 3, $[[BB0:BB[0-9_]+]]
+; OCTEON: bbit0   $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
-; MIPS64: bnez  $[[T0]], $[[BB0:BB[0-9_]+]]
+; MIPS64: bnez  $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
 define i64 @bbit032(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: bbit032:
-; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
+; OCTEON: bbit032 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
-; MIPS64: bnez    $[[T2]], $[[BB0:BB[0-9_]+]]
+; MIPS64: bnez    $[[T2]], [[BB0:(\$|.L)BB[0-9_]+]]
   %bit = and i64 %a, 34359738368
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
 define i64 @bbit1(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: bbit1:
-; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
+; OCTEON: bbit1 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
-; MIPS64: beqz  $[[T0]], $[[BB0:BB[0-9_]+]]
+; MIPS64: beqz  $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
   %res = icmp ne i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
 define i64 @bbit132(i64 %a) nounwind {
 entry:
 ; ALL-LABEL: bbit132:
-; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
+; OCTEON: bbit132 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
-; MIPS64: beqz    $[[T2]], $[[BB0:BB[0-9_]+]]
+; MIPS64: beqz    $[[T2]], [[BB0:(\$|.L)BB[0-9_]+]]
   %bit = and i64 %a, 34359738368
   %res = icmp ne i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }

test/CodeGen/Mips/private_label.ll

+; RUN: llc -march=mips < %s | FileCheck -check-prefix=O32 %s
+; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck -check-prefix=N32 %s
+; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck -check-prefix=N64 %s
+
+define void @labels() nounwind  {
+entry:
+  ; O32: $func_end
+  ; N32: .Lfunc_end
+  ; N64: .Lfunc_end
+  ret void
+}