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Differential D9337

[mips] Correct 128-bit shifts on 64-bit targets.
ClosedPublic

Authored by dsanders on Apr 29 2015, 3:34 AM.

Details

Reviewers
vkalintiris
Commits
rGf15e29680494: Merging r236099: --------------------------------------------------------------…
rG301f93776534: [mips] Correct 128-bit shifts on 64-bit targets.
rL236099: [mips] Correct 128-bit shifts on 64-bit targets.
Summary

The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 24608.Apr 29 2015, 3:34 AM
dsanders retitled this revision from to [mips] Correct 128-bit shifts on 64-bit targets..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added a reviewer: vkalintiris.
dsanders added subscribers: slthakur, mohit.bhakkad, Unknown Object (MLST).
vkalintiris accepted this revision.Apr 29 2015, 4:13 AM
vkalintiris edited edge metadata.

Thanks for fixing this. LGTM.

This revision is now accepted and ready to land.Apr 29 2015, 4:13 AM
dsanders closed this revision.Apr 29 2015, 5:32 AM

Revision Contents

PathSize
lib/
Target/
Mips/
10 lines
test/
CodeGen/
Mips/
llvm-ir/
12 lines
6 lines
6 lines

Diff 24608

lib/Target/Mips/MipsISelLowering.cpp

Show First 20 Lines • Show All 2,068 Lines • ▼ Show 20 Lines SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
DAG.getConstant(-1, DL, MVT::i32)); DAG.getConstant(-1, DL, MVT::i32));
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, DL, VT));
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32)); DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
DAG.getConstant(0, DL, VT), ShiftLeftLo); DAG.getConstant(0, DL, VT), ShiftLeftLo);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
SDValue Ops[2] = {Lo, Hi}; SDValue Ops[2] = {Lo, Hi};
return DAG.getMergeValues(Ops, DL); return DAG.getMergeValues(Ops, DL);
} }
Show All 22 LinesSDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
DAG.getConstant(1, DL, VT)); DAG.getConstant(1, DL, VT));
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
DL, VT, Hi, Shamt); DL, VT, Hi, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32)); DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
DAG.getConstant(31, DL, VT)); DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
IsSRA ? Shift31 : DAG.getConstant(0, DL, VT), ShiftRightHi); IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
SDValue Ops[2] = {Lo, Hi}; SDValue Ops[2] = {Lo, Hi};
return DAG.getMergeValues(Ops, DL); return DAG.getMergeValues(Ops, DL);
} }
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
SDValue Chain, SDValue Src, unsigned Offset) { SDValue Chain, SDValue Src, unsigned Offset) {
SDValue Ptr = LD->getBasePtr(); SDValue Ptr = LD->getBasePtr();
▲ Show 20 Lines • Show All 1,783 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/ashr.ll

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: ashr_i128: ; ALL-LABEL: ashr_i128:
; GP32: lw $25, %call16(__ashrti3)($gp) ; GP32: lw $25, %call16(__ashrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: nop ; M3: nop
; M3: dsra $2, $4, 31 ; M3: dsra $2, $4, 63
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrav $2, $4, $7 ; GP64-NOT-R6: dsrav $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31 ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
; 64R6: dsrav $[[T0:[0-9]+]], $4, $7 ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
; 64R6: sll $[[T1:[0-9]+]], $7, 0 ; 64R6: sll $[[T1:[0-9]+]], $7, 0
; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32 ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64
; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]] ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: dsra $[[T5:[0-9]+]], $4, 31 ; 64R6: dsra $[[T5:[0-9]+]], $4, 63
; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; 64R6: or $2, $[[T6]], $[[T4]] ; 64R6: or $2, $[[T6]], $[[T4]]
; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7 ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
; 64R6: dsll $[[T8:[0-9]+]], $4, 1 ; 64R6: dsll $[[T8:[0-9]+]], $4, 1
; 64R6: not $[[T9:[0-9]+]], $[[T1]] ; 64R6: not $[[T9:[0-9]+]], $[[T1]]
; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]] ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: or $3, $[[T13]], $[[T12]] ; 64R6: or $3, $[[T13]], $[[T12]]
%r = ashr i128 %a, %b %r = ashr i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/lshr.ll

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: lshr_i128: ; ALL-LABEL: lshr_i128:
; GP32: lw $25, %call16(__lshrti3)($gp) ; GP32: lw $25, %call16(__lshrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $2, $zero, 0 ; M3: daddiu $2, $zero, 0
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrlv $2, $4, $7 ; GP64-NOT-R6: dsrlv $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $zero, $1 ; GP64-NOT-R6: movn $2, $zero, $1
; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
; 64R6: dsll $[[T1:[0-9]+]], $4, 1 ; 64R6: dsll $[[T1:[0-9]+]], $4, 1
; 64R6: sll $[[T2:[0-9]+]], $7, 0 ; 64R6: sll $[[T2:[0-9]+]], $7, 0
; 64R6: not $[[T3:[0-9]+]], $[[T2]] ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]] ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7 ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $3, $[[T10]], $[[T8]] ; 64R6: or $3, $[[T10]], $[[T8]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $2, $[[T9]], $[[T7]] ; 64R6: seleqz $2, $[[T9]], $[[T7]]
%r = lshr i128 %a, %b %r = lshr i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/shl.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: shl_i128: ; ALL-LABEL: shl_i128:
; GP32: lw $25, %call16(__ashlti3)($gp) ; GP32: lw $25, %call16(__ashlti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: dsllv $[[T4:[0-9]+]], $4, $7 ; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $2, $[[T4]], $[[T7]] ; M3: or $2, $[[T4]], $[[T7]]
; M3: $[[BB0]]: ; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $3, $zero, 0 ; M3: daddiu $3, $zero, 0
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: $[[BB1]]: ; M3: $[[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $2, $[[T0]], $[[T4]] ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
; GP64-NOT-R6: dsllv $3, $5, $7 ; GP64-NOT-R6: dsllv $3, $5, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $2, $3, $[[T5]] ; GP64-NOT-R6: movn $2, $3, $[[T5]]
; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $3, $zero, $1 ; GP64-NOT-R6: movn $3, $zero, $1
; 64R6: dsllv $[[T0:[0-9]+]], $4, $7 ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7
; 64R6: dsrl $[[T1:[0-9]+]], $5, 1 ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1
; 64R6: sll $[[T2:[0-9]+]], $7, 0 ; 64R6: sll $[[T2:[0-9]+]], $7, 0
; 64R6: not $[[T3:[0-9]+]], $[[T2]] ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]] ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsllv $[[T9:[0-9]+]], $5, $7 ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $2, $[[T10]], $[[T8]] ; 64R6: or $2, $[[T10]], $[[T8]]
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $3, $[[T9]], $[[T7]] ; 64R6: seleqz $3, $[[T9]], $[[T7]]
%r = shl i128 %a, %b %r = shl i128 %a, %b
ret i128 %r ret i128 %r
} }