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Differential D9191

[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Needs ReviewPublic

Authored by jkolek on Apr 22 2015, 5:39 AM.

Details

Reviewers
zoran.jovanovic
Summary

This patch implements microMIPS LWLE, LWRE, SWLE and SWRE instructions.

Diff Detail

Event Timeline

jkolek updated this revision to Diff 24215.Apr 22 2015, 5:39 AM
jkolek retitled this revision from to [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions.
jkolek updated this object.
jkolek edited the test plan for this revision. (Show Details)
jkolek added a reviewer: zoran.jovanovic.
jkolek added a subscriber: Unknown Object (MLST).
hvarga added a subscriber: hvarga.Jun 16 2015, 1:14 AM
sdardis added a reviewer: sdardis.Apr 14 2016, 6:10 AM
sdardis resigned from this revision.Apr 15 2016, 1:54 AM
sdardis removed a reviewer: sdardis.

Can this patch be closed? Thanks.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
23 lines
14 lines
10 lines
test/
MC/
Disassembler/
Mips/
12 lines
12 lines
Mips/
12 lines
mips32r6/
9 lines
mips64r6/
8 lines
8 lines

Diff 24215

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Context not available.
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
Context not available.
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0x1ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
Context not available.

lib/Target/Mips/MicroMipsInstrFormats.td

Context not available.
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
} }
class STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
bits<5> rt;
bits<21> addr;
bits<32> Inst;
let Inst{31-26} = 0x18;
let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16};
let Inst{15-12} = type;
let Inst{11-9} = funct;
let Inst{8-0} = addr{8-0};
}
class CMov_F_I_FM_MM<bits<7> func> : MMArch { class CMov_F_I_FM_MM<bits<7> func> : MMArch {
bits<5> rd; bits<5> rd;
bits<5> rs; bits<5> rs;
Context not available.

lib/Target/Mips/MicroMipsInstrInfo.td

Context not available.
LWL_FM_MM<0x8>; LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>; LWL_FM_MM<0x9>;
let DecoderMethod = "DecodeMemMMImm9" in {
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0x6, 0x2>;
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0x6, 0x3>;
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0xa, 0x0>;
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
}
/// Load and Store Instructions - multiple /// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
Context not available.

test/MC/Disassembler/Mips/micromips.txt

Context not available.
# CHECK: movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3
0x84 0x34 0x84 0x34
# CHECK: swre $24, 5($3)
0x63 0x03 0xa2 0x05
# CHECK: swle $24, 5($3)
0x63 0x03 0xa0 0x05
# CHECK: lwre $24, 5($3)
0x63 0x03 0x66 0x05
# CHECK: lwle $24, 2($4)
0x63 0x04 0x64 0x02
Context not available.

test/MC/Disassembler/Mips/micromips_le.txt

Context not available.
# CHECK: movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3
0x34 0x84 0x34 0x84
# CHECK: swre $24, 5($3)
0x03 0x63 0x05 0xa2
# CHECK: swle $24, 5($3)
0x03 0x63 0x05 0xa0
# CHECK: lwre $24, 5($3)
0x03 0x63 0x05 0x66
# CHECK: lwle $24, 2($4)
0x04 0x63 0x02 0x64
Context not available.

test/MC/Mips/micromips-control-instructions.s

Context not available.
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Big endian # Big endian
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
Context not available.
# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
sdbbp sdbbp
sdbbp 34 sdbbp 34
Context not available.
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr
swre $24, 5($3)
swle $24, 5($3)
lwre $24, 5($3)
lwle $24, 2($4)
Context not available.

test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s

Context not available.
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Context not available.

test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s

Context not available.
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Context not available.

test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s

Context not available.
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Context not available.