[MachineLICM] Use newer model of register pressure sets.

[djasper]

Summary

TargetRegisterInfo::getRegPressureLimit has a note that it is an old model that relies on manually entered classes. Using the newer model of register pressure sets seems more appropriate. We might eventually even switch to lib/CodeGen/RegisterPressure.cpp, but we should probably do incremental changes here.

Using the newer model also makes it easier to take regmasks into account which is necessary to fix llvm.org/PR23143. I am currently also preparing a patch for that, but would like to do this switch independently.

[djasper]

Fix typo and exit early.

[qcolombet]

Hi Daniel,

Looks good to me with a couple a nitpicks. See my inline comments.

Basically, the comments and variables names should be updated to reflect that we use the RegPressureSet and not the register class anymore for the base identifier.

Thanks,
-Quentin

lib/CodeGen/MachineLICM.cpp

105

Update the comment to reflect that we now map the regPressureSet.

358

Change the name of the variable to NumRPS or something.
Right now, this is confusing.

1106

Change the name to RPIdAndCost or something along those lines.

1137

Ditto.

[djasper]

Addressed comments and submitted as r234880.

lib/CodeGen/MachineLICM.cpp

class MachineLICM : public MachineFunctionPass {
     }
 
     // Track 'estimated' register pressure.
     SmallSet<unsigned, 32> RegSeen;
     SmallVector<unsigned, 8> RegPressure;
 
     // Register pressure "limit" per register class. If the pressure
     // is higher than the limit, then it's considered high.
     SmallVector<unsigned, 8> RegLimit;
 
     // Register pressure on path leading from loop preheader to current BB.
     SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
 
     // For each opcode, keep a list of potential CSE instructions.
     DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
 
     enum {
private:
     void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode);
     void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
 
     /// SinkIntoLoop - Sink instructions into loops if profitable. This
     /// especially tries to prevent register spills caused by register pressure
     /// if there is little to no overhead moving instructions into loops.
     void SinkIntoLoop();
 
-    /// getRegisterClassIDAndCost - For a given register return the ID and cost
-    /// of its representative register class by reference.
-    void getRegisterClassIDAndCost(unsigned Reg, unsigned &RCId,
-                                   unsigned &RCCost) const;
-
     /// InitRegPressure - Find all virtual register references that are liveout
     /// of the preheader to initialize the starting "register pressure". Note
     /// this does not count live through (livein but not used) registers.
     void InitRegPressure(MachineBasicBlock *BB);
 
     /// calcRegisterCost - Calculate the additional register pressure that the
     /// registers used in MI cause.
     ///
bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
   if (PreRegAlloc)
     DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
   else
     DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
   DEBUG(dbgs() << MF.getName() << " ********\n");
 
   if (PreRegAlloc) {
     // Estimate register pressure during pre-regalloc pass.
-    unsigned NumRC = TRI->getNumRegClasses();
+    unsigned NumRC = TRI->getNumRegPressureSets();
     RegPressure.resize(NumRC);
     std::fill(RegPressure.begin(), RegPressure.end(), 0);
     RegLimit.resize(NumRC);
-    for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
-           E = TRI->regclass_end(); I != E; ++I)
-      RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
+    for (unsigned i = 0, e = NumRC; i != e; ++i)
+      RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
   }
 
   // Get our Loop information...
   MLI = &getAnalysis<MachineLoopInfo>();
   DT  = &getAnalysis<MachineDominatorTree>();
   AA  = &getAnalysis<AliasAnalysis>();
 
   SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
for (MachineInstr *I : Candidates) {
     B->splice(B->getFirstNonPHI(), Preheader, I);
   }
 }
 
 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
   return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
 }
 
-void MachineLICM::getRegisterClassIDAndCost(unsigned Reg, unsigned &RCId,
-                                            unsigned &RCCost) const {
-  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
-  MVT VT = *RC->vt_begin();
-  if (VT == MVT::Untyped) {
-    RCId = RC->getID();
-    RCCost = 1;
-  } else {
-    RCId = TLI->getRepRegClassFor(VT)->getID();
-    RCCost = TLI->getRepRegClassCostFor(VT);
-  }
-}
-
 /// InitRegPressure - Find all virtual register references that are liveout of
 /// the preheader to initialize the starting "register pressure". Note this
 /// does not count live through (livein but not used) registers.
 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
   std::fill(RegPressure.begin(), RegPressure.end(), 0);
 
   // If the preheader has only a single predecessor and it ends with a
   // fallthrough or an unconditional branch, then scan its predecessor for live
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
     if (!MO.isReg() || MO.isImplicit())
       continue;
     unsigned Reg = MO.getReg();
     if (!TargetRegisterInfo::isVirtualRegister(Reg))
       continue;
 
     // FIXME: It seems bad to use RegSeen only for some of these calculations.
     bool isNew = ConsiderSeen ? RegSeen.insert(Reg).second : false;
-    unsigned RCId, RCCost;
-    getRegisterClassIDAndCost(Reg, RCId, RCCost);
-    int PriorCost = 0;
-    if (Cost.find(RCId) != Cost.end())
-      PriorCost = Cost[RCId];
+    const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+
+    RegClassWeight W = TRI->getRegClassWeight(RC);
+    int RCCost = 0;
     if (MO.isDef())
-      Cost[RCId] = PriorCost + RCCost;
+      RCCost = W.RegWeight;
     else {
       bool isKill = isOperandKill(MO, MRI);
       if (isNew && !isKill && ConsiderUnseenAsDef)
         // Haven't seen this, it must be a livein.
-        Cost[RCId] = PriorCost + RCCost;
+        RCCost = W.RegWeight;
       else if (!isNew && isKill)
-        Cost[RCId] = PriorCost - RCCost;
+        RCCost = -W.RegWeight;
+    }
+    const int *PS = TRI->getRegClassPressureSets(RC);
+    for (; *PS != -1; ++PS) {
+      if (Cost.find(*PS) != Cost.end())
+        Cost[*PS] = RCCost;
+      else
+        Cost[*PS] += RCCost;
     }
   }
   return Cost;
 }
 
 /// isLoadFromGOTOrConstantPool - Return true if this machine instruction
 /// loads from global offset table or constant pool.
 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
   return isCheap;
 }
 
 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
 /// if hoisting an instruction of the given cost matrix can cause high
 /// register pressure.
 bool MachineLICM::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
                                           bool CheapInstr) {
   for (const auto &ClassAndCost : Cost) {
     if (ClassAndCost.second <= 0)
       continue;
 
     unsigned Class = ClassAndCost.first;
     int Limit = RegLimit[Class];
 
     // Don't hoist cheap instructions if they would increase register pressure,
     // even if we're under the limit.

 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
   // First compute the 'cost' of the instruction, i.e. its contribution
   // to register pressure.
   auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/false,
                                /*ConsiderUnseenAsDef=*/false);
 
   // Update register pressure of blocks from loop header to current block.
   for (auto &RP : BackTrace)
     for (const auto &ClassAndCost : Cost)
       RP[ClassAndCost.first] += ClassAndCost.second;
 }
 
 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
 /// the given loop invariant.
 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
   if (MI.isImplicitDef())
     return true;