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[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.
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Authored by tomatabacu on Mar 12 2015, 4:35 AM.

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Summary

This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.

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Event Timeline

tomatabacu updated this revision to Diff 21817.Mar 12 2015, 4:35 AM
tomatabacu retitled this revision from to [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction..
tomatabacu updated this object.
tomatabacu edited the test plan for this revision. (Show Details)
tomatabacu added a reviewer: dsanders.
tomatabacu added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Mar 13 2015, 9:48 AM
dsanders edited edge metadata.

LGTM

lib/Target/Mips/MipsInstrInfo.td
1583–1584

Just to mention it: This isn't quite right for the 64-bit ISA's but it will do the correct thing as far as the assembler is concerned by virtue of having the same opcode. It's not a problem with any tools we currently develop so no changes required.

This revision is now accepted and ready to land.Mar 13 2015, 9:48 AM
tomatabacu closed this revision.Mar 17 2015, 6:20 AM