[WIP] Support inline assembly memory constraints that do not behave like 'm'.

[dsanders]

This is going to be split up into multiple patches.

include/llvm/CodeGen/SelectionDAGISel.h

public:
   /// PostprocessISelDAG() - This hook allows the target to hack on the graph
   /// right after selection.
   virtual void PostprocessISelDAG() {}
 
   /// Select - Main hook targets implement to select a node.
   virtual SDNode *Select(SDNode *N) = 0;
 
   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
-  /// addressing mode, according to the specified constraint code.  If this does
+  /// addressing mode, according to the specified constraint.  If this does
   /// not match or is not implemented, return true.  The resultant operands
   /// (which will appear in the machine instruction) should be added to the
   /// OutOps vector.
   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                            char ConstraintCode,
+                                            unsigned ConstraintID,
                                             std::vector<SDValue> &OutOps) {
     return true;
   }
 
   /// IsProfitableToFold - Returns true if it's profitable to fold the specific
   /// operand node N of U during instruction selection that starts at Root.
   virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
 

include/llvm/IR/InlineAsm.h

public:
   // Methods for support type inquiry through isa, cast, and dyn_cast:
   static inline bool classof(const Value *V) {
     return V->getValueID() == Value::InlineAsmVal;
   }
 
   
   // These are helper methods for dealing with flags in the INLINEASM SDNode
   // in the backend.
-  
+  //
+  // The encoding of the flag word is currently:
+  //   Bit 31 - Set if the flags represent a matching operand.
+  //            Clear if they represent a register class.
+  //   If bits 2-0 are Kind_Mem:
+  //     Bits 31 - 0
+  //     Bits 30-16 - A Constraint_* value representing the constraint code.
+  //   Else if bit 31 is set:
+  //     Bits 30-16 - The operand number to match.
+  //   Else if bit 31 is clear:
+  //     Bits 30-16 - The register class for the constraint.
+  //   Bits 15-3 - The number of operands to the SDNode associated with this
+  //               inline assembly operand.
+  //   Bits 2-0 - The kind of operand (see the Kind_* values).
   enum : uint32_t {
     // Fixed operands on an INLINEASM SDNode.
     Op_InputChain = 0,
     Op_AsmString = 1,
     Op_MDNode = 2,
     Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
     Op_FirstOperand = 4,
 
enum : uint32_t {
     // bits is the kind:
     Kind_RegUse = 1,             // Input register, "r".
     Kind_RegDef = 2,             // Output register, "=r".
     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
     Kind_Clobber = 4,            // Clobbered register, "~r".
     Kind_Imm = 5,                // Immediate.
     Kind_Mem = 6,                // Memory operand, "m".
 
+    // Memory constraint codes. 
+    // These could be tablegenerated but there's little need to do that since
+    // there's plenty of space in the encoding to support the union of all
+    // constraint codes.
+    Constraint_Unknown = 0,
+    Constraint_i,
+    Constraint_m,
+    Constraint_o,
+    Constraint_v,
+    Constraint_Q,
+    Constraint_R,
+    Constraint_S,
+    Constraint_T,
+    Constraint_X,
+    Constraint_Uv,
+    Constraint_Z,
+    Constraint_Zy,
+    Constraint_ZC,
+    Constraints_Max = Constraint_ZC,
+    Constraints_ShiftAmount = 16,
+
     Flag_MatchingOperand = 0x80000000
   };
   
   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
     return Kind | (NumOps << 3);
   }
public:
   static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
     // Store RC + 1, reserve the value 0 to mean 'no register class'.
     ++RC;
     assert(RC <= 0x7fff && "Too large register class ID");
     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
     return InputFlag | (RC << 16);
   }
 
+  /// Augment an existing flag word returned by getFlagWord with the constraint
+  /// code for a memory constraint.
+  static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
+    assert(Constraint <= 0x7fff && "Too large memory constraint ID");
+    assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
+    return InputFlag | (Constraint << Constraints_ShiftAmount);
+  }
+
   static unsigned getKind(unsigned Flags) {
     return Flags & 7;
   }
 
   static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
   static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
   static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
   static bool isRegDefEarlyClobberKind(unsigned Flag) {
     return getKind(Flag) == Kind_RegDefEarlyClobber;
   }
   static bool isClobberKind(unsigned Flag) {
     return getKind(Flag) == Kind_Clobber;
   }
+  static unsigned getMemoryConstraintID(unsigned Flag) {
+    assert(isMemKind(Flag));
+    return (Flag >> Constraints_ShiftAmount) & 0x7fff;
+  }
 
   /// getNumOperandRegisters - Extract the number of registers field from the
   /// inline asm operand flag.
   static unsigned getNumOperandRegisters(unsigned Flag) {
     return (Flag & 0xffff) >> 3;
   }
 
   /// isUseOperandTiedToDef - Return true if the flag of the inline asm

include/llvm/Target/TargetLowering.h

 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Target/TargetCallingConv.h"
 #include "llvm/Target/TargetMachine.h"
 #include <climits>
 #include <map>
 #include <vector>
+#include "llvm/Support/Debug.h"
 
 namespace llvm {
   class CallInst;
   class CCState;
   class FastISel;
   class FunctionLoweringInfo;
   class ImmutableCallSite;
   class IntrinsicInst;
public:
   /// pointer.
   ///
   /// This should only be used for C_Register constraints.  On error, this
   /// returns a register number of 0 and a null register class pointer.
   virtual std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                const std::string &Constraint, MVT VT) const;
 
+  /// Convert a memory constraint (e.g. "m") into an InlineAsm::Constraint_*
+  /// value.
+  /// Unsupported constraints should return InlineAsm::Constraint_Unknown.
+  virtual unsigned getInlineAsmMemConstraint(const std::string Constraint) const {
+    if (Constraint == "m") return InlineAsm::Constraint_m;
+    if (Constraint == "o") return InlineAsm::Constraint_o;
+    if (Constraint == "v") return InlineAsm::Constraint_v;
+    if (Constraint == "X") return InlineAsm::Constraint_X;
+    errs() << "Unknown Constraint " << Constraint << "\n";
+    return InlineAsm::Constraint_Unknown;
+  }
+
   /// Try to replace an X constraint, which matches anything, with another that
   /// has more specific requirements based on the type of the corresponding
   /// operand.  This returns null if there is no replacement to make.
   virtual const char *LowerXConstraint(EVT ConstraintVT) const;
 
   /// Lower the specified operand into the Ops vector.  If it is invalid, don't
   /// add anything to Ops.
   virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
 
     switch (OpInfo.Type) {
     case InlineAsm::isOutput: {
       if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
           OpInfo.ConstraintType != TargetLowering::C_Register) {
         // Memory output, or 'other' output (e.g. 'X' constraint).
         assert(OpInfo.isIndirect && "Memory output must be indirect operand");
 
+        unsigned ConstraintID =
+            TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
+        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+               "Unknown memory constraint");
+
         // Add information to the INLINEASM node to know about this output.
         unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
-        AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
-                                                        TLI.getPointerTy()));
+        OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
+        AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
         AsmNodeOperands.push_back(OpInfo.CallOperand);
         break;
       }
 
       // Otherwise, this is a register or register class output.
 
       // Copy the output from the appropriate register.  Find a register that
       // we can use.
case InlineAsm::isInput: {
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
         assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
         assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
                "Memory operands expect pointer values");
 
+        unsigned ConstraintID =
+            TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
+        assert(ConstraintID != InlineAsm::Constraint_Unknown &&
+               "Unknown memory constraint");
+
         // Add information to the INLINEASM node to know about this input.
         unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
-        AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
-                                                        TLI.getPointerTy()));
+        ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
+        AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
         AsmNodeOperands.push_back(InOperandVal);
         break;
       }
 
       assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
               OpInfo.ConstraintType == TargetLowering::C_Register) &&
              "Unknown constraint type!");
 

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (!InlineAsm::isMemKind(Flags)) {
       Ops.insert(Ops.end(), InOps.begin()+i,
                  InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
       i += InlineAsm::getNumOperandRegisters(Flags) + 1;
     } else {
       assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
              "Memory operand with multiple values?");
       // Otherwise, this is a memory operand.  Ask the target to select it.
       std::vector<SDValue> SelOps;
-      if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
+      if (SelectInlineAsmMemoryOperand(InOps[i+1],
+                                       InlineAsm::getMemoryConstraintID(Flags),
+                                       SelOps))
         report_fatal_error("Could not match memory address.  Inline asm"
                            " failure!");
 
       // Add this to the output node.
       unsigned NewFlags =
         InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
       Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
       Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

bool runOnMachineFunction(MachineFunction &MF) override {
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   SDNode *Select(SDNode *Node) override;
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    char ConstraintCode,
+                                    unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   SDNode *SelectMLAV64LaneV128(SDNode *N);
   SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
   bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
   bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
   bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
   bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {

 // If so Imm will receive the 32 bit value.
 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
                                   uint64_t &Imm) {
   return N->getOpcode() == Opc &&
          isIntImmediate(N->getOperand(1).getNode(), Imm);
 }
 
 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
-    const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
-  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
+    const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
+
   // Require the address to be in a register.  That is safe for all AArch64
   // variants and it is hard to do anything much smarter without knowing
   // how the operand is used.
   OutOps.push_back(Op);
   return false;
 }
 
 /// SelectArithImmed - Select an immediate value that can be represented as

lib/Target/AArch64/AArch64ISelLowering.h

private:
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                const std::string &Constraint,
                                MVT VT) const override;
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
+  unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+    if (Constraint == "Q")
+      return InlineAsm::Constraint_Q;
+    return TargetLowering::getInlineAsmMemConstraint(Constraint);
+  }
+
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
   bool mayBeEmittedAsTailCall(CallInst *CI) const override;
   bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
                               ISD::MemIndexedMode &AM, bool &IsInc,
                               SelectionDAG &DAG) const;
   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
                                  ISD::MemIndexedMode &AM,
                                  SelectionDAG &DAG) const override;

lib/Target/ARM/ARMISelDAGToDAG.cpp

private:
   SDNode *SelectABSOp(SDNode *N);
 
   SDNode *SelectInlineAsm(SDNode *N);
 
   SDNode *SelectConcatVector(SDNode *N);
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   // Form pairs of consecutive R, S, D, or Q registers.
   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
 
SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
   SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
       CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
   New->setNodeId(-1);
   return New.getNode();
 }
 
 
 bool ARMDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
-  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
+
   // Require the address to be in a register.  That is safe for all ARM
   // variants and it is hard to do anything much smarter without knowing
   // how the operand is used.
   OutOps.push_back(Op);
   return false;
 }
 
 /// createARMISelDag - This pass converts a legalized DAG into a
 /// ARM-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
                                      CodeGenOpt::Level OptLevel) {
   return new ARMDAGToDAGISel(TM, OptLevel);
 }

lib/Target/ARM/ARMISelLowering.h

public:
     ConstraintWeight getSingleConstraintMatchWeight(
       AsmOperandInfo &info, const char *constraint) const override;
 
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  const std::string &Constraint,
                                  MVT VT) const override;
 
+    unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+      if (Constraint == "Q")
+        return InlineAsm::Constraint_Q;
+      if (Constraint == "Uv")
+        return InlineAsm::Constraint_Uv;
+      return TargetLowering::getInlineAsmMemConstraint(Constraint);
+    }
+
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     /// true it means one of the asm constraint of the inline asm instruction
     /// being processed is 'm'.
     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                       std::vector<SDValue> &Ops,
                                       SelectionDAG &DAG) const override;
 

lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

public:
   bool runOnMachineFunction(MachineFunction &MF) override {
     Subtarget = &MF.getSubtarget<HexagonSubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    char ConstraintCode,
+                                    unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
   bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
 
   SDNode *SelectLoad(SDNode *N);
   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
                                         SDLoc dl);
bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
 
   Base = Addr;
   Offset = CurDAG->getTargetConstant(0, MVT::i32);
   return true;
 }
 
 
 bool HexagonDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
+
   SDValue Op0, Op1;
 
-  switch (ConstraintCode) {
-  case 'o':   // Offsetable.
-  case 'v':   // Not offsetable.
-  default: return true;
-  case 'm':   // Memory.
+  switch (ConstraintID) {
+  default:
+  case InlineAsm::Constraint_m:   // Memory.
     if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   return false;

lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

public:
     const char *getPassName() const override {
       return "MSP430 DAG->DAG Pattern Instruction Selection";
     }
 
     bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
 
-    bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+    bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override;
 
     // Include the pieces autogenerated from the target description.
   #include "MSP430GenDAGISel.inc"
 
   private:
     SDNode *Select(SDNode *N) override;
     SDNode *SelectIndexedLoad(SDNode *Op);
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
                                          0/*AM.SymbolFlags*/);
   else
     Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
 
   return true;
 }
 
 bool MSP430DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
   SDValue Op0, Op1;
-  switch (ConstraintCode) {
-  default: return true;
-  case 'm':   // memory
+  switch (ConstraintID) {
+  default:
+  case InlineAsm::Constraint_m:   // memory
     if (!SelectAddr(Op, Op0, Op1))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   return false;

lib/Target/Mips/MipsAsmPrinter.cpp

bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
   MachineBasicBlock::const_iterator I = Pred->end();
   while (I != Pred->begin() && !(--I)->isTerminator()) ;
 
   return !I->isBarrier();
 }
 
 // Print out an operand for an inline asm expression.
 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
-                                     unsigned AsmVariant,const char *ExtraCode,
+                                     unsigned AsmVariant, const char *ExtraCode,
                                      raw_ostream &O) {
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
     const MachineOperand &MO = MI->getOperand(OpNum);
     switch (ExtraCode[0]) {
     default:
bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
   printOperand(MI, OpNum, O);
   return false;
 }
 
 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                            unsigned OpNum, unsigned AsmVariant,
                                            const char *ExtraCode,
                                            raw_ostream &O) {
-  int Offset = 0;
+  const MachineOperand &BaseMO = MI->getOperand(OpNum);
+  const MachineOperand &OffsetMO = MI->getOperand(OpNum+1);
+  assert(OffsetMO.isImm() && "unexpected inline asm memory operand");
+  int Offset = OffsetMO.getImm();
+
   // Currently we are expecting either no ExtraCode or 'D'
   if (ExtraCode) {
     if (ExtraCode[0] == 'D')
-      Offset = 4;
+      Offset += 4;
+    // FIXME: M = high order
+    // FIXME: L = low order
     else
       return true; // Unknown modifier.
   }
 
-  const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isReg() && "unexpected inline asm memory operand");
-  O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
+  assert(BaseMO.isReg() && "unexpected inline asm memory operand");
+  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
 
   return false;
 }
 
 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
                                   raw_ostream &O) {
   const DataLayout *DL = TM.getDataLayout();
   const MachineOperand &MO = MI->getOperand(opNum);

lib/Target/Mips/MipsISelDAGToDAG.h

private:
   // getImm - Return a target constant with the specified value.
   inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
     return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
   }
 
   virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    char ConstraintCode,
+                                    unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 };
 }
 
 #endif

lib/Target/Mips/MipsISelDAGToDAG.cpp

if (ResNode == nullptr || ResNode == Node)
     DEBUG(Node->dump(CurDAG));
   else
     DEBUG(ResNode->dump(CurDAG));
   DEBUG(errs() << "\n");
   return ResNode;
 }
 
 bool MipsDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
-  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
+  // All memory constraints can at least manage plain addresses but
+  // MipsDAGToDAGISel subclasses should be more specific.
   OutOps.push_back(Op);
+  OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
   return false;
 }

lib/Target/Mips/MipsISelLowering.h

 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
 
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "Mips.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/IR/Function.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetLowering.h"
 #include <deque>
 #include <string>
 
 namespace llvm {
   namespace MipsISD {
     enum NodeType {
       // Start the numbering from where ISD NodeType finishes.
private:
     std::pair<unsigned, const TargetRegisterClass *>
     parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
 
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  const std::string &Constraint,
                                  MVT VT) const override;
 
+    unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+      if (Constraint == "R")
+        return InlineAsm::Constraint_R;
+      if (Constraint == "ZC")
+        return InlineAsm::Constraint_ZC;
+      return TargetLowering::getInlineAsmMemConstraint(Constraint);
+    }
+
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     /// true it means one of the asm constraint of the inline asm instruction
     /// being processed is 'm'.
     void LowerAsmOperandForConstraint(SDValue Op,
                                       std::string &Constraint,
                                       std::vector<SDValue> &Ops,
                                       SelectionDAG &DAG) const override;

lib/Target/Mips/MipsISelLowering.cpp

switch (Constraint[0]) {
       case 'c':
       case 'l':
       case 'x':
         return C_RegisterClass;
       case 'R':
         return C_Memory;
     }
   }
+
+  if (Constraint == "ZC")
+    return C_Memory;
+
   return TargetLowering::getConstraintType(Constraint);
 }
 
 /// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// and the current alternative constraint selected.
 TargetLowering::ConstraintWeight
 MipsTargetLowering::getSingleConstraintMatchWeight(

lib/Target/Mips/MipsSEISelDAGToDAG.h

private:
 
   std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
 
   void processFunctionAfterISel(MachineFunction &MF) override;
 
   // Insert instructions to initialize the global base register in the
   // first MBB of the function.
   void initGlobalBaseReg(MachineFunction &MF);
+
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                    unsigned ConstraintID,
+                                    std::vector<SDValue> &OutOps) override;
 };
 
 FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
 
 }
 
 #endif

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

case ISD::BUILD_VECTOR: {
     return std::make_pair(true, Res);
   }
 
   }
 
   return std::make_pair(false, nullptr);
 }
 
+bool MipsSEDAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+                             std::vector<SDValue> &OutOps) {
+  SDValue Base, Offset, Alias;
+
+  switch (ConstraintID) {
+  case InlineAsm::Constraint_ZC:
+    // FIXME: This implementation is actually wrong but it's good enough to test
+    // that constraints other than 'm' work.
+    // It should be selecting between different sized immediates according to
+    // the subtarget.
+    if (this->selectAddrRegImm12(Op, Base, Offset)) {
+      OutOps.push_back(Base);
+      OutOps.push_back(Offset);
+      return false;
+    }
+
+  // FIXME: All other memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
+  default:
+  case InlineAsm::Constraint_m:
+    break;
+  }
+
+  OutOps.push_back(Op);
+  OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
+  return false;
+}
+
 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
   return new MipsSEDAGToDAGISel(TM);
 }

lib/Target/NVPTX/NVPTXISelDAGToDAG.h

public:
   // Pass Name
   const char *getPassName() const override {
     return "NVPTX DAG->DAG Pattern Instruction Selection";
   }
   bool runOnMachineFunction(MachineFunction &MF) override;
   const NVPTXSubtarget *Subtarget;
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    char ConstraintCode,
+                                    unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 private:
 // Include the pieces autogenerated from the target description.
 #include "NVPTXGenDAGISel.inc"
 
   SDNode *Select(SDNode *N) override;
   SDNode *SelectIntrinsicNoChain(SDNode *N);
   SDNode *SelectIntrinsicChain(SDNode *N);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
   if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
     return (PT->getAddressSpace() == spN);
   return false;
 }
 
 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 /// inline asm expressions.
 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
-    const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
+    const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
   SDValue Op0, Op1;
-  switch (ConstraintCode) {
+  switch (ConstraintID) {
   default:
-    return true;
-  case 'm': // memory
+  case InlineAsm::Constraint_m: // memory
     if (SelectDirectAddr(Op, Op0)) {
       OutOps.push_back(Op0);
       OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
       return false;
     }
     if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
       OutOps.push_back(Op0);
       OutOps.push_back(Op1);
       return false;
     }
     break;
   }
   return true;
 }

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
     }
 
     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     /// inline asm expressions.  It is always correct to compute the value into
     /// a register.  The case of adding a (possibly relocatable) constant to a
     /// register can be improved, but it is wrong to substitute Reg+Reg for
     /// Reg in an asm, because the load or store opcode would have to change.
     bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                      char ConstraintCode,
+                                      unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override {
       // We need to make sure that this one operand does not end up in r0
       // (because we might end up lowering this as 0(%op)).
       const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
       const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
       SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
       SDValue NewOp =
         SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,

lib/Target/PowerPC/PPCISelLowering.h

public:
     ConstraintWeight getSingleConstraintMatchWeight(
       AsmOperandInfo &info, const char *constraint) const override;
 
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  const std::string &Constraint,
                                  MVT VT) const override;
 
+    unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+      if (Constraint == "Z")
+        return InlineAsm::Constraint_Z;
+      if (Constraint == "Zy")
+        return InlineAsm::Constraint_Zy;
+      return TargetLowering::getInlineAsmMemConstraint(Constraint);
+    }
+
     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
     /// function arguments in the caller parameter area.  This is the actual
     /// alignment, not its logarithm.
     unsigned getByValTypeAlignment(Type *Ty) const override;
 
     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     /// vector.  If it is invalid, don't add anything to Ops.
     void LowerAsmOperandForConstraint(SDValue Op,

lib/Target/Sparc/SparcISelDAGToDAG.cpp

public:
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
   bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
 
   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
   /// inline asm expressions.
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                    char ConstraintCode,
+                                    unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   const char *getPassName() const override {
     return "SPARC DAG->DAG Pattern Instruction Selection";
   }
 
   // Include the pieces autogenerated from the target description.
 #include "SparcGenDAGISel.inc"
SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
   return SelectCode(N);
 }
 
 
 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 /// inline asm expressions.
 bool
 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                                char ConstraintCode,
+                                                unsigned ConstraintID,
                                                 std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
   SDValue Op0, Op1;
-  switch (ConstraintCode) {
-  default: return true;
-  case 'm':   // memory
+  switch (ConstraintID) {
+  default:
+  case InlineAsm::Constraint_m:   // memory
    if (!SelectADDRrr(Op, Op0, Op1))
      SelectADDRri(Op, Op0, Op1);
    break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   return false;
 }
 
 /// createSparcISelDag - This pass converts a legalized DAG into a
 /// SPARC-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
   return new SparcDAGToDAGISel(TM);
 }

lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

public:
 
   // Override MachineFunctionPass.
   const char *getPassName() const override {
     return "SystemZ DAG->DAG Pattern Instruction Selection";
   }
 
   // Override SelectionDAGISel.
   SDNode *Select(SDNode *Node) override;
-  bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
   // Include the pieces autogenerated from the target description.
   #include "SystemZGenDAGISel.inc"
 };
 } // end anonymous namespace
 
 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
DEBUG(errs() << "=> ";
           ResNode->dump(CurDAG);
         errs() << "\n";
         );
   return ResNode;
 }
 
 bool SystemZDAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op,
-                             char ConstraintCode,
+                             unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
-  assert(ConstraintCode == 'm' && "Unexpected constraint code");
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
+
   // Accept addresses with short displacements, which are compatible
   // with Q, R, S and T.  But keep the index operand for future expansion.
   SDValue Base, Disp, Index;
   if (!selectBDXAddr(SystemZAddressingMode::FormBD,
                      SystemZAddressingMode::Disp12Only,
                      Op, Base, Disp, Index))
     return true;
   OutOps.push_back(Base);
   OutOps.push_back(Disp);
   OutOps.push_back(Index);
   return false;
 }

lib/Target/SystemZ/SystemZISelLowering.h

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
                                       bool *Fast) const override;
   bool isTruncateFree(Type *, Type *) const override;
   bool isTruncateFree(EVT, EVT) const override;
   const char *getTargetNodeName(unsigned Opcode) const override;
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                const std::string &Constraint,
                                MVT VT) const override;
+
+  unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+    if (Constraint == "Q")
+      return InlineAsm::Constraint_Q;
+    if (Constraint == "R")
+      return InlineAsm::Constraint_R;
+    if (Constraint == "S")
+      return InlineAsm::Constraint_S;
+    if (Constraint == "T")
+      return InlineAsm::Constraint_T;
+    return TargetLowering::getInlineAsmMemConstraint(Constraint);
+  }
+
   TargetLowering::ConstraintType
     getConstraintType(const std::string &Constraint) const override;
   TargetLowering::ConstraintWeight
     getSingleConstraintMatchWeight(AsmOperandInfo &info,
                                    const char *constraint) const override;
   void LowerAsmOperandForConstraint(SDValue Op,
                                     std::string &Constraint,
                                     std::vector<SDValue> &Ops,

lib/Target/X86/X86ISelDAGToDAG.cpp

private:
     bool TryFoldLoad(SDNode *P, SDValue N,
                      SDValue &Base, SDValue &Scale,
                      SDValue &Index, SDValue &Disp,
                      SDValue &Segment);
 
     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     /// inline asm expressions.
     bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                      char ConstraintCode,
+                                      unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override;
 
     void EmitSpecialCodeForMain();
 
     inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
                                    SDValue &Scale, SDValue &Index,
                                    SDValue &Disp, SDValue &Segment) {
       Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
DEBUG(dbgs() << "=> ";
         else
           ResNode->dump(CurDAG);
         dbgs() << '\n');
 
   return ResNode;
 }
 
 bool X86DAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
   SDValue Op0, Op1, Op2, Op3, Op4;
-  switch (ConstraintCode) {
-  case 'o':   // offsetable        ??
-  case 'v':   // not offsetable    ??
-  default: return true;
-  case 'm':   // memory
+  switch (ConstraintID) {
+  default:
+  case InlineAsm::Constraint_m:   // memory
     if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);

lib/Target/X86/X86ISelLowering.h

public:
     /// (e.g. {edx}), return the register number and the register class for the
     /// register.  This should only be used for C_Register constraints.  On
     /// error, this returns a register number of 0.
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  const std::string &Constraint,
                                  MVT VT) const override;
 
+    unsigned getInlineAsmMemConstraint(const std::string Constraint) const override {
+      // FIXME: Should 'i' really be handled here? It's not a memory constraint
+      //        but tests fail if we don't handle it here.
+      if (Constraint == "i")
+        return InlineAsm::Constraint_i;
+      return TargetLowering::getInlineAsmMemConstraint(Constraint);
+    }
+
     /// Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
 
     /// Return true if the specified immediate is legal
     /// icmp immediate, that is the target has icmp instructions which can
     /// compare a register against the immediate without having to materialize
     /// the immediate into a register.

lib/Target/XCore/XCoreISelDAGToDAG.cpp

inline bool immMskBitp(SDNode *inN) const {
       int msksize = 32 - countLeadingZeros(value);
       return (msksize >= 1 && msksize <= 8) ||
               msksize == 16 || msksize == 24 || msksize == 32;
     }
 
     // Complex Pattern Selectors.
     bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
 
-    bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+    bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override;
 
     const char *getPassName() const override {
       return "XCore DAG->DAG Pattern Instruction Selection";
     } 
     
     // Include the pieces autogenerated from the target description.
   #include "XCoreGenDAGISel.inc"
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
       return true;
     }
   }
   return false;
 }
 
 bool XCoreDAGToDAGISel::
-SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
+  // FIXME: All memory constraints currently behave like 'm'.
+  //        This is presumably wrong but it preserves the existing behaviour.
   SDValue Reg;
-  switch (ConstraintCode) {
-  default: return true;
-  case 'm': // Memory.
+  switch (ConstraintID) {
+  default:
+  case InlineAsm::Constraint_m: // Memory.
     switch (Op.getOpcode()) {
     default: return true;
     case XCoreISD::CPRelativeWrapper:
       Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
       break;
     case XCoreISD::DPRelativeWrapper:
       Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
       break;

test/CodeGen/Mips/inlineasm_constraint_ZC.ll

+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+@data = global [2048 x i32] zeroinitializer
+
+define void @ZC_no_offset(i32* %p) nounwind {
+entry:
+  ; CHECK-LABEL: ZC_no_offset:
+
+  ; Check ZC on a plain pointer
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([2048 x i32]* @data, i32 0, i32 0))
+  ; CHECK: lw      $[[BASEPTR:[0-9]+]], %got(data)($1)
+  ; CHECK: #APP
+  ; CHECK: lw ${{[0-9]+}}, 0($[[BASEPTR]])
+  ; CHECK: #NO_APP
+  ret void
+}
+
+define void @ZC_in_range_offset(i32* %p) nounwind {
+entry:
+  ; CHECK-LABEL: ZC_in_range_offset:
+
+  ; Check ZC on an offset  pointer
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([2048 x i32]* @data, i32 0, i32 1))
+  ; CHECK: lw      $[[BASEPTR:[0-9]+]], %got(data)($1)
+  ; CHECK: #APP
+  ; CHECK: lw ${{[0-9]+}}, 4($[[BASEPTR]])
+  ; CHECK: #NO_APP
+  ret void
+}
+
+define void @ZC_out_of_range_offset(i32* %p) nounwind {
+entry:
+  ; CHECK-LABEL: ZC_out_of_range_offset:
+
+  ; Check ZC on an offset  pointer
+  call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([2048 x i32]* @data, i32 0, i32 1024))
+  ; CHECK: lw      $[[BASEPTR:[0-9]+]], %got(data)($1)
+  ; CHECK: addiu   $[[PTR:[0-9]+]], $[[BASEPTR]], 4096
+  ; CHECK: #APP
+  ; CHECK: lw ${{[0-9]+}}, 0($[[PTR]])
+  ; CHECK: #NO_APP
+  ret void
+}