[mips] Refactor saved-registers bitmask creation in MipsAsmPrinter::printSavedRegsBitmask. NFC.

[tomatabacu]

Summary

Make the code more readable by fusing the for-loops together and explicitly checking for each register class.

Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector.

[dsanders]

LGTM with a style nit

lib/Target/Mips/MipsAsmPrinter.cpp

272

Nit: Please use 'else if' instead of continue.

[tomatabacu]

Used 'else if' instead of 'continue'.
Rebased.

[tomatabacu]

Missed a 'continue'.

lib/Target/Mips/MipsAsmPrinter.cpp

void MipsAsmPrinter::printSavedRegsBitmask() {
   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
   // size of stack area to which FP callee-saved regs are saved.
   unsigned CPURegSize = Mips::GPR32RegClass.getSize();
   unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
   unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
   bool HasAFGR64Reg = false;
   unsigned CSFPRegsSize = 0;
-  unsigned i, e = CSI.size();
-
-  // Set FPU Bitmask.
-  for (i = 0; i != e; ++i) {
-    unsigned Reg = CSI[i].getReg();
-    if (Mips::GPR32RegClass.contains(Reg))
-      break;
 
+  for (const auto &I : CSI) {
+    unsigned Reg = I.getReg();
     unsigned RegNum = TRI->getEncodingValue(Reg);
-    if (Mips::AFGR64RegClass.contains(Reg)) {
-      FPUBitmask |= (3 << RegNum);
-      CSFPRegsSize += AFGR64RegSize;
-      HasAFGR64Reg = true;
-      continue;
-    }
 
+    // If it's a floating point register, set the FPU Bitmask.
+    // If it's a general purpose register, set the CPU Bitmask.
+    if (Mips::FGR32RegClass.contains(Reg)) {
       FPUBitmask |= (1 << RegNum);
       CSFPRegsSize += FGR32RegSize;
-  }
-
-  // Set CPU Bitmask.
-  for (; i != e; ++i) {
-    unsigned Reg = CSI[i].getReg();
-    unsigned RegNum = TRI->getEncodingValue(Reg);
+    } else if (Mips::AFGR64RegClass.contains(Reg)) {
+      FPUBitmask |= (3 << RegNum);
+      CSFPRegsSize += AFGR64RegSize;
+      HasAFGR64Reg = true;
+    } else if (Mips::GPR32RegClass.contains(Reg))
       CPUBitmask |= (1 << RegNum);
   }
 
   // FP Regs are saved right below where the virtual frame pointer points to.
   FPUTopSavedRegOff = FPUBitmask ?
     (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
 
   // CPU Regs are saved below FP Regs.
   CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;